Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits. - Anupam Basu; Thomas Charles Wilson; Dilip K. Banerji; Jayanti C. Majithia (Great Lakes Symposium on VLSI, 1991)

Test plan generation and concurrent scheduling of tests in the presence of conflicts. - Thomas Charles Wilson; Anupam Basu; Dilip K. Banerji; Jayanti C. Majithia (Great Lakes Symposium on VLSI, 1991)

An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test. - Anupam Basu; Thomas Charles Wilson; Dilip K. Banerji; Jayanti C. Majithia (VLSI Design, 1992)

MinMux: a new approach for global minimization of multiplexers in interconnect synthesis. - Thomas Charles Wilson; Manoj K. Garg; R. Deadman; Ben Halley; Dilip K. Banerji (Great Lakes Symposium on VLSI, 1993)

An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. - Thomas Charles Wilson; Nilanjan Mukherjee; Manoj K. Garg; Dilip K. Banerji (VLSI Design, 1993)

An ILP-based approach to code generation. - Thomas Charles Wilson; Gary William Grewal; Shawn Henshall; Dilip K. Banerji (Code Generation for Embedded Processors, 1994)

An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis. - Thomas Charles Wilson; Gary William Grewal; Dilip K. Banerji (ICCD, 1994)

An integrated approach to retargetable code generation. - Thomas Charles Wilson; Gary Gréwal; Ben Halley; Dilip K. Banerji (HLSS, 1994)

An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis. - Thomas Charles Wilson; Nilanjan Mukherjee; Manoj K. Garg; Dilip K. Banerji (VLSI Design, 1995)

Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation. - J. Shu; Thomas Charles Wilson; Dilip K. Banerji (VLSI Design, 1996)

A Modified Approach to Test Plan Generation for Combinational Logic Blocks. - Anupam Basu; Dilip K. Banerji; Amit Basu; Thomas Charles Wilson; Jayanti C. Majithia (VLSI Design, 1996)

An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design. - Gary William Grewal; Thomas Charles Wilson (VLSI Design, 1997)

Shake And Bake: A Method of Mapping Code to Irregular DSPs. - Thomas Charles Wilson; Gary William Grewal (VLSI Design, 1997)

An Enhanced Genetic Algorithm for Solving the High-Level Synthesis Problems of Scheduling, Allocation, and Binding. - Gary William Grewal; Thomas Charles Wilson (Int. J. Comput. Intell. Appl., 2001)

An Enhanced Genetic Algorithm Approach to the Channel Assignment Problem in Mobile Cellular Networks. - Gary William Grewal; Thomas Charles Wilson; Christopher W. Nell (AI, 2002)

Mapping Reference Code to Irregular DSPS within the Retargetable, Optimizing Compiler Cogen(T). - Gary William Grewal; Thomas Charles Wilson (Int. J. Comput. Intell. Appl., 2003)

An EGA approach to the compile-time assignment of data to multiple memories in digital-signal processors. - Gary Gréwal; Thomas Charles Wilson; Andrew Morton (SIGARCH Comput. Archit. News, 2003)

Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees. - Gary William Grewal; Thomas Charles Wilson; Ming Xu; Dilip K. Banerji (VLSI Design, 2004)