A multi-Gbps unrolled hardware list decoder for a systematic polar code. - Pascal Giard; Alexios Balatsoukas-Stimming; Thomas Christoph Müller; Andreas Peter Burg; Claude Thibeault; Warren J. Gross (ACSSC, 2016)

DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. - Jeremy Constantin; Andrea Bonetti; Adam Teman; Thomas Christoph Müller; Lorenz Schmid; Andreas Burg 001 (ESSCIRC, 2016)

A 594 Gbps LDPC Decoder Based on Finite-Alphabet Message Passing. - Reza Ghanaatian; Alexios Balatsoukas-Stimming; Thomas Christoph Müller; Michael Meidlinger; Gerald Matz; Adam Teman; Andreas Burg 001 (CoRR, 2017)

A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors. - Davide Rossi; Igor Loi; Antonio Pullini; Thomas Christoph Müller; Andreas Burg 001; Francesco Conti 001; Luca Benini; Philippe Flatresse (IEEE Des. Test, 2017)

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. - Pascal Giard; Alexios Balatsoukas-Stimming; Thomas Christoph Müller; Andrea Bonetti; Claude Thibeault; Warren J. Gross; Philippe Flatresse; Andreas Burg 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2017)

A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing. - Reza Ghanaatian; Alexios Balatsoukas-Stimming; Thomas Christoph Müller; Michael Meidlinger; Gerald Matz; Adam Teman; Andreas Burg 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller. - Pasquale Davide Schiavone; Simone Machetti; Miguel Peón-Quirós; José Miranda; Benoît W. Denkinger; Thomas Christoph Müller; Rubén Rodríguez Álvarez; Saverio Nasturzio; David Atienza Alonso (CF, 2023)

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators. - Simone Machetti; Pasquale Davide Schiavone; Thomas Christoph Müller; Miguel Peón-Quirós; David Atienza (CoRR, 2024)