Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip. - Thomas Edison Yu; Tomokazu Yoneda; Krishnendu Chakrabarty; Hideo Fujiwara (ATS, 2007)

Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. - Thomas Edison Yu; Tomokazu Yoneda; Danella Zhao; Hideo Fujiwara (VTS, 2007)

Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths. - Thomas Edison Yu; Tomokazu Yoneda; Satoshi Ohtake; Hideo Fujiwara (ATS, 2008)

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips. - Thomas Edison Yu; Tomokazu Yoneda; Krishnendu Chakrabarty; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2008)

Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints. - Thomas Edison Yu; Tomokazu Yoneda; Danella Zhao; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2008)

Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. - Thomas Edison Yu; Tomokazu Yoneda; Krishnendu Chakrabarty; Hideo Fujiwara (ASP-DAC, 2009)

RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC. - Fawnizu Azmadi Hussin; Thomas Edison Yu; Tomokazu Yoneda; Hideo Fujiwara (APCCAS, 2010)