Analysis and optimization for dynamic read stability in 28nm SRAM bitcells. - Ahmed T. Elthakeb; Thomas Haine; Denis Flandre; Yehea Ismail; Hamdy Abd Elhamid; David Bol (ISCAS, 2015)

CAMEL: An Ultra-Low-Power VGA CMOS Imager based on a Time-Based DPS Array. - Thomas Haine; François Stas; Guerric de Streel; Cecilia Gimeno; Denis Flandre; David Bol (ICDSC, 2016)

An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation. - Thomas Haine; Quoc-Khoi Nguyen; François Stas; Ludovic Moreau; Denis Flandre; David Bol (ESSCIRC, 2017)

Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics. - Thomas Haine; Johan Segers; Denis Flandre; David Bol (DATE, 2018)

Large array-based circuits in ULV SoCs: design and statistical assessment of SRAMs and CMOS imagers. - Thomas Haine (2018)

A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode. - David Bol; Maxime Schramme; Ludovic Moreau; Thomas Haine; Pengcheng Xu 002; Charlotte Frenkel; Remi Dekimpe; François Stas; Denis Flandre (ISSCC, 2019)

SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode. - David Bol; Maxime Schramme; Ludovic Moreau; Pengcheng Xu 002; Rémi Dekimpe; Roghayeh Saeidi; Thomas Haine; Charlotte Frenkel; Denis Flandre (IEEE J. Solid State Circuits, 2021)