A 14 ns 256 K*1 CMOS SRAM with multiple test modes. - Peter H. Voss; Leo C. M. G. Pfennings; Cathal G. Phelan; Cormac M. O'Connell; Thomas J. Davies; Hans Ontrop; Simon A. Bell; Roelof H. W. Salters (IEEE J. Solid State Circuits, 1989)