Design validation of .18 μm 1 GHz cache and register arrays. - Doug Malone; Paul Bunce; Joe DellaPietro; John Davis; James Dawson; Thomas J. Knips; Don Plass; Phil Pritzlaff; Kenneth Reyer (CICC, 2000)

A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. - John Davis; Don Plass; Paul Bunce; Yuen H. Chan; Antonio Pelella; Rajiv V. Joshi; A. Chen; William V. Huott; Thomas J. Knips; Pradip Patel; K. Lo; Eric Fluhr (ISSCC, 2006)

7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor. - John Davis; Paul Bunce; Diana M. Henderson; Yuen H. Chan; Uma Srinivasan 002; Daniel Rodko; Pradip Patel; Thomas J. Knips; Tobias Werner 001 (ISSCC, 2013)

17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access. - Gregory Fredeman; Donald W. Plass; Abraham Mathews; Kenneth Reyer; Thomas J. Knips; Thomas Miller; Elizabeth L. Gerhard; Dinesh Kannambadi; Chris Paone; Dongho Lee; Daniel Rainey 002; Michael A. Sperling; et al. (ISSCC, 2015)

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. - Gregory Fredeman; Donald W. Plass; Abraham Mathews; Janakiraman Viraraghavan; Kenneth Reyer; Thomas J. Knips; Thomas Miller; Elizabeth L. Gerhard; Dinesh Kannambadi; Chris Paone; Dongho Lee; Daniel Rainey 002; et al. (IEEE J. Solid State Circuits, 2016)