Minimizing the problem of logic testing by the interaction of a design group with user-oriented facilities. - Manuel Correia; Donald Cossman; Franco Putzolu; Thomas J. Snethen (DAC, 1970)

Simulator-oriented fault test generator. - Thomas J. Snethen (DAC, 1977)

Design of an Efficient Weighted-Random-Pattern Generation System. - Rohit Kapur; Srinivas Patil; Thomas J. Snethen; Thomas W. Williams (ITC, 1994)

A weighted random pattern test generation system. - Rohit Kapur; Srinivas Patil; Thomas J. Snethen; Thomas W. Williams (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Advanced microprocessor test strategy and methodology. - William V. Huott; Timothy J. Koprowski; Bryan J. Robbins; Mary P. Kusko; Stephen Pateras; Dale E. Hoffman; Timothy G. McNamara; Thomas J. Snethen (IBM J. Res. Dev., 1997)

Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip. - Mary P. Kusko; Bryan J. Robbins; Thomas J. Snethen; Peilin Song; Thomas G. Foote; William V. Huott (ITC, 1998)

A Simplified Method for Testing the IBM Pipeline Partial-Scan Microprocessor. - Xinghao Chen 004; Thomas J. Snethen; Joe Swenton; Ron Walther (Asian Test Symposium, 1999)

A SmartBIST Variant with Guaranteed Encoding. - Bernd Könemann; Carl Barnhart; Brion L. Keller; Thomas J. Snethen; Owen Farnsworth; Donald L. Wheater (Asian Test Symposium, 2001)

Using Programmable On-Product Clock Generation (OPCG) for Delay Test. - Brion L. Keller; Anis Uzzaman; Bibo Li; Thomas J. Snethen (ATS, 2007)

Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation. - Anis Uzzaman; Bibo Li; Thomas J. Snethen; Brion L. Keller; Gary Grise (ITC, 2007)

Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. - Anis Uzzaman; Brion L. Keller; Thomas J. Snethen; Kazuhiko Iwasaki; Masayuki Arai (J. Low Power Electron., 2009)

Low cost at-speed testing using On-Product Clock Generation compatible with test compression. - Brion L. Keller; Krishna Chakravadhanula; Brian Foutz; Vivek Chickermane; R. Malneedi; Thomas J. Snethen; Vikram Iyengar; David E. Lackey; Gary Grise (ITC, 2010)

Efficient testing of hierarchical core-based SOCs. - Brion L. Keller; Krishna Chakravadhanula; Brian Foutz; Vivek Chickermane; Akhil Garg 001; Richard Schoonover; James Sage; Don Pearl; Thomas J. Snethen (ITC, 2014)