Standard-cell-based design methodology for high-performance support chips. - Bernhard Kick; Ulrich Baur; Jürgen Koehl; Thomas Ludwig 004; Thomas Pflueger (IBM J. Res. Dev., 1997)

A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset. - Jürgen Koehl; Ulrich Baur; Thomas Ludwig 004; Bernhard Kick; Thomas Pflueger (DATE, 1998)

Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS. - Amaury Nève; Denis Flandre; Helmut Schettler; Thomas Ludwig 004; Gerhard Hellner (ISLPED, 2002)

Scaling beyond the 65 nm node with FinFET-DGCMOS. - Edward J. Nowak; Thomas Ludwig 004; Ingo Aller; Jakub Kedzierski; M. Leong; BethAnn Rainey; Matthew J. Breitwisch; V. Gemhoefer; Joachim Keinert; David M. Fried (CICC, 2003)

Power-delay product minimization in high-performance 64-bit carry-select adders. - Amaury Nève; Helmut Schettler; Thomas Ludwig 004; Denis Flandre (IEEE Trans. Very Large Scale Integr. Syst., 2004)