Thinwire protocol for connecting personal computers to the Internet. - David J. Farber; Gary S. Delp; Thomas M. Conte (RFC, 1984)

Comparing Software and Hardware Schemes For Reducing the Cost of Branches. - Wen-mei W. Hwu; Thomas M. Conte; Pohua P. Chang (ISCA, 1989)

A Simulation Study of Simultaneous Vector Prefetch Performance in Multiprocessor Memory Subsystems (Extended Abstract). - Wen-mei W. Hwu; Thomas M. Conte (SIGMETRICS, 1989)

Benchmark Characterization. - Thomas M. Conte; Wen-mei W. Hwu (Computer, 1991)

A brief survey of benchmark usage in the architecture community. - Thomas M. Conte; Wen-mei W. Hwu (SIGARCH Comput. Archit. News, 1991)

Tradeoffs in processor/memory interfaces for superscalar processors. - Thomas M. Conte (MICRO, 1992)

Systematic prototyping of superscalar computer architectures. - Thomas M. Conte; Wen-mei W. Hwu (RSP, 1992)

Systematic Computer Architecture Prototyping - Thomas M. Conte (1992)

Determining Cost-Effective Multiple Issue Processor Designs. - Thomas M. Conte; William H. Mangione-Smith (ICCD, 1993)

The Effect of Code Expanding Optimizations on Instruction Cache Design. - William Y. Chen; Pohua P. Chang; Thomas M. Conte; Wen-mei W. Hwu (IEEE Trans. Computers, 1993)

Fast Simulation of Computer Architectures: Introduction. - Thomas M. Conte; Charles E. Gimarc (HICSS (1), 1994)

Using branch handling hardware to support profile-driven optimization. - Thomas M. Conte; Burzin A. Patel; J. Stan Cox (MICRO, 1994)

The Susceptibility of Programs to Context Switching. - Wen-mei W. Hwu; Thomas M. Conte (IEEE Trans. Computers, 1994)

A technique to determine power-efficient, high-performance superscalar processors. - Thomas M. Conte; Kishore N. Menezes; Sumedh W. Sathaye (HICSS (1), 1995)

Commercializing profile-driven optimization. - J. Stan Cox; David P. Howell; Thomas M. Conte (HICSS (1), 1995)

Optimization of Instruction Fetch Mechanisms for High Issue Rates. - Thomas M. Conte; Kishore N. Menezes; Patrick M. Mills; Burzin A. Patel (ISCA, 1995)

Dynamic rescheduling: a technique for object code compatibility in VLIW architectures. - Thomas M. Conte; Sumedh W. Sathaye (MICRO, 1995)

Advances in Benchmarking Techniques: New Standards and Quantitative Metrics. - Thomas M. Conte; Wen-mei W. Hwu (Adv. Comput., 1995)

Reducing State Loss For Effective Trace Sampling of Superscalar Processors. - Thomas M. Conte; Mary Ann Hirsch; Kishore N. Menezes (ICCD, 1996)

Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. - Thomas M. Conte; Sanjeev Banerjia; Sergei Y. Larin; Kishore N. Menezes; Sumedh W. Sathaye (MICRO, 1996)

Accurate and Practical Profile-driven Compilation Using the Profile Buffer. - Thomas M. Conte; Kishore N. Menezes; Mary Ann Hirsch (MICRO, 1996)

A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures. - Thomas M. Conte; Sumedh W. Sathaye; Sanjeev Banerjia (MICRO, 1996)

Bipartitioning for Hybrid FPGA-Software Simulatio. - Ashutosh Singla; Thomas M. Conte (VLSI Design, 1996)

Importance of Profiling and Compatibility. - Thomas M. Conte (ACM Comput. Surv., 1996)

Hardware-Based Profiling: An Effective Technique for Profile-Driven Optimization. - Thomas M. Conte; Burzin A. Patel; Kishore N. Menezes; J. Stan Cox (Int. J. Parallel Program., 1996)

Path Prediction for High Issue-Rate Processors. - Kishore N. Menezes; Sumedh W. Sathaye; Thomas M. Conte (IEEE PACT, 1997)

Treegion Scheduling for Highly Parallel Processors. - Sanjeev Banerjia; William A. Havanki; Thomas M. Conte (Euro-Par, 1997)

Combining General-Purpose and Multimedia in One Package: Challenges and Opportunities. - Thomas M. Conte; Andrew Wolfe (HICSS (1), 1997)

Challenges to Combining General-Purpose and Multimedia Processors. - Thomas M. Conte; Pradeep K. Dubey; Matthew D. Jennings; Ruby B. Lee; Alex Peleg; Salliah Rathnam; Michael S. Schlansker; Peter Song; Andrew Wolfe (Computer, 1997)

Compilers for Instruction-Level Parallelism. - Michael S. Schlansker; Thomas M. Conte; James C. Dehnert; Kemal Ebcioglu; Jesse Zhixi Fang; Carol L. Thompson (Computer, 1997)

Optimization of VLIW compatibility systems employing dynamic rescheduling. - Thomas M. Conte; Sumedh W. Sathaye (Int. J. Parallel Program., 1997)

A Fast Interrupt Handling Scheme for VLIW Processors. - Emre Özer 001; Sumedh W. Sathaye; Kishore N. Menezes; Sanjeev Banerjia; Matthew D. Jennings; Thomas M. Conte (IEEE PACT, 1998)

Value Speculation Scheduling for High Performance Processors. - Chao-ying Fu; Matthew D. Jennings; Sergei Y. Larin; Thomas M. Conte (ASPLOS, 1998)

Treegion Scheduling for Wide Issue Processors. - William A. Havanki; Sanjeev Banerjia; Thomas M. Conte (HPCA, 1998)

Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures. - Emre Özer 001; Sanjeev Banerjia; Thomas M. Conte (MICRO, 1998)

Performance Analysis and Its Impact on Design. - Pradip Bose; Thomas M. Conte (Computer, 1998)

Subword extensions for video processing on mobile systems. - Matthew D. Jennings; Thomas M. Conte (IEEE Concurr., 1998)

MPS: Miss-Path Scheduling for Multiple-Issue Processors. - Sanjeev Banerjia; Sumedh W. Sathaye; Kishore N. Menezes; Thomas M. Conte (IEEE Trans. Computers, 1998)

Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation. - Thomas M. Conte; Mary Ann Hirsch; Wen-mei W. Hwu (IEEE Trans. Computers, 1998)

Dynamically Programmable Cache Evaluation and Virtualization. - Mouna Nakkar; David G. Bentlage; John Harding; David Schwartz; Paul D. Franzon; Thomas M. Conte (FPGA, 1999)

Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. - Sergei Y. Larin; Thomas M. Conte (MICRO, 1999)

Editor's Introduction. - Thomas M. Conte; Wen-mei W. Hwu; Mark Smotherman (Int. J. Parallel Program., 1999)

Editors' Introduction. - Thomas M. Conte; Wen-mei W. Hwu; Mark Smotherman (Int. J. Parallel Program., 1999)

Challenges in processor modeling and validation [Guest Editors?? introduction]. - Pradip Bose; Thomas M. Conte; Todd M. Austin (IEEE Micro, 1999)

A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization. - Kim M. Hazelwood; Thomas M. Conte (IEEE PACT, 2000)

Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility. - Thomas M. Conte; Sumedh W. Sathaye (IEEE Trans. Computers, 2000)

System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. - Thomas M. Conte; Kishore N. Menezes; Sumedh W. Sathaye; Mark C. Toburen (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors. - Emre Özer 001; Thomas M. Conte; Saurabh Sharma (HiPC, 2001)

Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors. - Huiyang Zhou; Matthew D. Jennings; Thomas M. Conte (LCPC, 2001)

Code Size Efficiency in Global Scheduling for ILP Processors. - Huiyang Zhou; Thomas M. Conte (Interaction between Compilers and Computer Architectures, 2002)

Choosing the Brain(s) of an Embedded System. - Thomas M. Conte (Computer, 2002)

Detecting Global Stride Locality in Value Streams. - Huiyang Zhou; Jill Flanagan; Thomas M. Conte (ISCA, 2003)

Modeling Value Speculation: An Optimal Edge Selection Problem. - Chao-ying Fu; Jill T. Bodine; Thomas M. Conte (IEEE Trans. Computers, 2003)

Adaptive mode control: A static-power-efficient cache design. - Huiyang Zhou; Mark C. Toburen; Eric Rotenberg; Thomas M. Conte (ACM Trans. Embed. Comput. Syst., 2003)

Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems. - Alessio Bechini; Thomas M. Conte; Cosimo Antonio Prete (IEEE Micro, 2004)

Insight, not (random) numbers. - Thomas M. Conte (ISPASS, 2005)

Configurable string matching hardware for speeding up intrusion detection. - Monther Aldwairi; Thomas M. Conte; Paul D. Franzon (SIGARCH Comput. Archit. News, 2005)

Spectral prefetcher: An effective mechanism for L2 cache prefetching. - Saurabh Sharma; Jesse G. Beu; Thomas M. Conte (ACM Trans. Archit. Code Optim., 2005)

Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction. - Huiyang Zhou; Thomas M. Conte (IEEE Trans. Computers, 2005)

High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm. - Emre Özer 001; Thomas M. Conte (IEEE Trans. Parallel Distributed Syst., 2005)

Keynote: Insight, Not (Random) Numbers: An Embedded Perspective. - Thomas M. Conte (HiPEAC, 2007)

Combining cluster sampling with single pass methods for efficient sampling regimen design. - Paul D. Bryan; Thomas M. Conte (ICCD, 2007)

Reverse State Reconstruction for Sampled Microarchitectural Simulation. - Paul D. Bryan; Michel C. Rosier; Thomas M. Conte (ISPASS, 2007)

Energy-aware opcode design. - Balaji V. Iyer; Jason A. Poovey; Thomas M. Conte (ICCD, 2008)

A Power Model for Register-Sharing Structures. - Balaji V. Iyer; Thomas M. Conte (DIPES, 2008)

On power and energy trends of IEEE 802.11n PHY. - Balaji V. Iyer; Thomas M. Conte (MSWiM, 2009)

Embedded Multicore Processors and Systems. - Markus Levy; Thomas M. Conte (IEEE Micro, 2009)

A Benchmark Characterization of the EEMBC Benchmark Suite. - Jason A. Poovey; Thomas M. Conte; Markus Levy; Shay Gal-On (IEEE Micro, 2009)

Energy efficient Phase Change Memory based main memory for future high performance systems. - Rishiraj A. Bheda; Jason A. Poovey; Jesse G. Beu; Thomas M. Conte (IGCC, 2011)

Parallel Pattern Detection for Architectural Improvements. - Jason A. Poovey; Brian P. Railing; Thomas M. Conte (HotPar, 2011)

Manager-client pairing: a framework for implementing coherence hierarchies. - Jesse G. Beu; Michel C. Rosier; Thomas M. Conte (MICRO, 2011)

Extrapolation Pitfalls When Evaluating Limited Endurance Memory. - Rishiraj A. Bheda; Jesse G. Beu; Brian P. Railing; Thomas M. Conte (MASCOTS, 2012)

Accelerating Multi-threaded Application Simulation through Barrier-Interval Time-Parallelism. - Paul D. Bryan; Jason A. Poovey; Jesse G. Beu; Thomas M. Conte (MASCOTS, 2012)

Designing Configurable, Modifiable and Reusable Components for Simulation of Multicore Systems. - Jun Wang 077; Jesse G. Beu; Sudhakar Yalamanchili; Tom Conte 001 (SC Companion, 2012)

High-speed formal verification of heterogeneous coherence hierarchies. - Jesse G. Beu; Jason A. Poovey; Eric R. Hein; Thomas M. Conte (HPCA, 2013)

Manifold: A parallel simulation framework for multicore systems. - Jun Wang 077; Jesse G. Beu; Rishiraj A. Bheda; Tom Conte 001; Zhenjiang Dong; Chad D. Kersey; Mitchelle Rasquinha; George F. Riley; William J. Song; He Xiao; Peng Xu; Sudhakar Yalamanchili (ISPASS, 2014)

Rebooting Computing and Low-Power Image Recognition Challenge. - Yung-Hsiang Lu; Alan M. Kadin; Alexander C. Berg; Thomas M. Conte; Erik P. DeBenedictis; Rachit Garg; Ganesh Gingade; Bichlien Hoang; Yongzhen Huang; Boxun Li; Jingyu Liu 004; Wei Liu 015; et al. (ICCAD, 2015)

A Time of Change. - Tom Conte 001 (Computer, 2015)

The Computer Society Must Change. - Thomas M. Conte (Computer, 2015)

Rebooting Computing: New Strategies for Technology Scaling. - Thomas M. Conte; Elie K. Track; Erik DeBenedictis (Computer, 2015)

Contech: Efficiently Generating Dynamic Task Graphs for Arbitrary Parallel Programs. - Brian P. Railing; Eric R. Hein; Thomas M. Conte (ACM Trans. Archit. Code Optim., 2015)

Energy efficiency limits of logic and memory. - Sapan Agarwal; Jeanine E. Cook; Erik DeBenedictis; Michael P. Frank; Gert Cauwenberghs; Sriseshan Srikanth; Bobin Deng; Eric R. Hein; Paul G. Rabbat; Thomas M. Conte (ICRC, 2016)

Computationally-redundant energy-efficient processing for y'all (CREEPY). - Bobin Deng; Sriseshan Srikanth; Eric R. Hein; Paul G. Rabbat; Thomas M. Conte; Erik DeBenedictis; Jeanine E. Cook (ICRC, 2016)

Improving DRAM Bandwidth Utilization with MLP-Aware OS Paging. - Rishiraj A. Bheda; Thomas M. Conte; Jeffrey S. Vetter (MEMSYS, 2016)

A Brief Survey of Non-Residue Based Computational Error Correction. - Sriseshan Srikanth; Bobin Deng; Thomas M. Conte (CoRR, 2016)

Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C. - Erik P. DeBenedictis; Jeanine E. Cook; Sriseshan Srikanth; Thomas M. Conte (HPEC, 2017)

The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing. - Sriseshan Srikanth; Thomas M. Conte; Erik P. DeBenedictis; Jeanine E. Cook (ICRC, 2017)

Rebooting Computing: The Road Ahead. - Thomas M. Conte; Erik P. DeBenedictis; Paolo A. Gargini; Elie K. Track (Computer, 2017)

Sustaining Moore's Law with 3D Chips. - Erik P. DeBenedictis; Mustafa Badaroglu; An Chen; Thomas M. Conte; Paolo A. Gargini (Computer, 2017)

Challenges to Keeping the Computer Industry Centered in the US. - Thomas M. Conte; Erik P. DeBenedictis; R. Stanley Williams; Mark D. Hill (CoRR, 2017)

Architectures for the Post-Moore Era. - Jeffrey S. Vetter; Erik P. DeBenedictis; Thomas M. Conte (IEEE Micro, 2017)

Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures. - Sriseshan Srikanth; Paul G. Rabbat; Eric R. Hein; Bobin Deng; Thomas M. Conte; Erik DeBenedictis; Jeanine E. Cook; Michael P. Frank (HPCA, 2018)

An Initial Characterization of the Emu Chick. - Eric R. Hein; Tom Conte 001; Jeffrey Young 001; Srinivas Eswar; Jiajia Li 001; Patrick Lavin; Richard W. Vuduc; E. Jason Riedy (IPDPS Workshops, 2018)

Tackling memory access latency through DRAM row management. - Sriseshan Srikanth; Lavanya Subramanian; Sreenivas Subramoney; Thomas M. Conte; Hong Wang 003 (MEMSYS, 2018)

Rebooting Computers to Avoid Meltdown and Spectre. - Thomas M. Conte; Erik P. DeBenedictis; Avi Mendelson; Dejan S. Milojicic (Computer, 2018)

Standards: Roadmapping Computer Technology Trends Enlightens Industry. - F. D. Wright; Thomas M. Conte (Computer, 2018)

Iterative Modulo Scheduling. - Onur Mutlu; Scott A. Mahlke; Thomas M. Conte; Wen-Mei W. Hwu (IEEE Micro, 2018)

Extending Moore's Law via Computationally Error-Tolerant Computing. - Bobin Deng; Sriseshan Srikanth; Eric R. Hein; Thomas M. Conte; Erik DeBenedictis; Jeanine E. Cook; Michael P. Frank (ACM Trans. Archit. Code Optim., 2018)

Experimental Insights from the Rogues Gallery. - Jeffrey S. Young 001; E. Jason Riedy; Thomas M. Conte; Vivek Sarkar; Prasanth Chatarasi; Sriseshan Srikanth (ICRC, 2019)

Application Performance of Physical System Simulations. - Vladimir Getov; Peter M. Kogge; Thomas M. Conte (PARCO, 2019)

Wrangling Rogues: A Case Study on Managing Experimental Post-Moore Architectures. - Will Powell; E. Jason Riedy; Jeffrey S. Young 001; Thomas M. Conte (PEARC, 2019)

Thermodynamic Computing. - Tom Conte 001; Erik DeBenedictis; Natesh Ganesh; Todd Hylton; John Paul Strachan; R. Stanley Williams; Alexander A. Alemi; Lee Altenberg; Gavin E. Crooks; James P. Crutchfield; Lídia del Rio; Josh Deutsch; et al. (CoRR, 2019)

A microbenchmark characterization of the Emu chick. - Jeffrey S. Young 001; Eric R. Hein; Srinivas Eswar; Patrick Lavin; Jiajia Li 001; E. Jason Riedy; Richard W. Vuduc; Tom Conte 001 (Parallel Comput., 2019)

Special Session: Exploring the Ultimate Limits of Adiabatic Circuits. - Michael P. Frank; Robert W. Brocato; Thomas M. Conte; Alexander H. Hsia; Anirudh Jain; Nancy A. Missert; Karpur Shukla; Brian D. Tierney (ICCD, 2020)

Intrepydd: performance, productivity, and portability for data science application kernels. - Tong Zhou 007; Jun Shirako; Anirudh Jain; Sriseshan Srikanth; Thomas M. Conte; Richard W. Vuduc; Vivek Sarkar (Onward!, 2020)

Evolving Methods for Evaluating and Disseminating Computing Research. - Benjamin Zorn 001; Tom Conte 001; Keith Marzullo; Suresh Venkatasubramanian (CoRR, 2020)

MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams. - Sriseshan Srikanth; Anirudh Jain; Joseph M. Lennon; Thomas M. Conte; Erik DeBenedictis; Jeanine E. Cook (ACM Trans. Archit. Code Optim., 2020)

Programming Strategies for Irregular Algorithms on the Emu Chick. - Eric R. Hein; Srinivas Eswar; Abdurrahman Yasar; Jiajia Li 001; Jeffrey S. Young 001; Thomas M. Conte; Ümit V. Çatalyürek; Richard W. Vuduc; E. Jason Riedy; Bora Uçar (ACM Trans. Parallel Comput., 2020)

Enabling a Programming Environment for an Experimental Ion Trap Quantum Testbed. - Austin J. Adams; Elton Pinto; Jeffrey Young 001; Creston D. Herold; Alexander J. McCaskey; Eugene F. Dumitrescu; Thomas M. Conte (ICRC, 2021)

A vision to compute like nature: thermodynamically. - Todd Hylton; Thomas M. Conte; Mark D. Hill (Commun. ACM, 2021)

Advancing Computing's Foundation of US Industry & Society. - Thomas M. Conte; Ian T. Foster; William Gropp; Mark D. Hill (CoRR, 2021)

SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads. - Sriseshan Srikanth; Anirudh Jain; Thomas M. Conte; Erik P. DeBenedictis; Jeanine E. Cook (ACM Trans. Archit. Code Optim., 2021)

"Smarter" NICs for faster molecular dynamics: a case study. - Sara Karamati; Clayton Hughes; K. Scott Hemmert; Ryan E. Grant; Whit Schonbein; Scott Levy; Thomas M. Conte; Jeffrey Young 001; Richard W. Vuduc (IPDPS, 2022)

Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems. - Bobin Deng; Sriseshan Srikanth; Anirudh Jain; Thomas M. Conte; Erik DeBenedictis; Jeanine E. Cook (IEEE Trans. Computers, 2022)

Enabling Multi-threading in Heterogeneous Quantum-Classical Programming Models. - Akihiro Hayashi; Austin J. Adams; Jeffrey Young 001; Alexander J. McCaskey; Eugene F. Dumitrescu; Vivek Sarkar; Thomas M. Conte (IPDPS Workshops, 2023)

The Invention of Electronic Digital Computing - Plenary Panel Summary. - John Vincent Atanasoff; Gordon Bell; Kiril L. Boyanov; Charles G. Call; Carl K. Chang; Thomas M. Conte; Vladimir Getov; John L. Gustafson; Hironori Kasahara; Dejan S. Milojicic; Michael R. Williams (JVA, 2023)

Status Update on the IEEE Rebooting Computing Initiative. - Thomas M. Conte (JVA, 2023)

5 Year Update to the Next Steps in Quantum Computing. - Kenneth R. Brown; Fred Chong; Kaitlin N. Smith; Tom Conte 001; Austin J. Adams; Aniket S. Dalvi; Christopher Kang; Joshua Viszlai (CoRR, 2024)

Qwerty: A Basis-Oriented Quantum Programming Language. - Austin J. Adams; Sharjeel Khan; Jeffrey S. Young 001; Thomas M. Conte (CoRR, 2024)

RASSM: Residue-based Acceleration of Single Sparse Matrix Computation via Adaptive Tiling. - Anirudh Jain; Pulkit Gupta; Thomas M. Conte (ASPLOS (1), 2025)

ASDF: A Compiler for Qwerty, a Basis-Oriented Quantum Programming Language. - Austin J. Adams; Sharjeel Khan; Arjun S. Bhamra; Ryan R. Abusaada; Anthony M. Cabrera; Cameron C. Hoechst; Travis S. Humble; Jeffrey S. Young 001; Thomas M. Conte (CGO, 2025)

A Blueprint for Q-CS1, an Introductory Quantum Programming Course. - Austin J. Adams; Rodrigo Borela; Jeffrey S. Young 001; Thomas M. Conte (SIGCSE (2), 2025)