Compaction of ATPG-generated test sequences for sequential circuits. - Rabindra K. Roy; Thomas M. Niermann; Janak H. Patel; Jacob A. Abraham; Resve A. Saleh (ICCAD, 1988)

HITEC: a test generation package for sequential circuits. - Thomas M. Niermann; Janak H. Patel (EURO-DAC, 1991)

Methods for Reducing Events in Sequential Circuit Fault Simulation. - Elizabeth M. Rudnick; Thomas M. Niermann; Janak H. Patel (ICCAD, 1991)

Techniques for sequential circuit automatic test generation - Thomas M. Niermann (1991)

PROOFS: a fast, memory-efficient sequential circuit fault simulator. - Thomas M. Niermann; Wu-Tung Cheng; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Test compaction for sequential circuits. - Thomas M. Niermann; Rabindra K. Roy; Janak H. Patel; Jacob A. Abraham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Sequential Circuit Test Generation in a Genetic Algorithm Framework. - Elizabeth M. Rudnick; Janak H. Patel; Gary S. Greenstein; Thomas M. Niermann (DAC, 1994)

A genetic algorithm framework for test generation. - Elizabeth M. Rudnick; Janak H. Patel; Gary S. Greenstein; Thomas M. Niermann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)