Recursive Variable Expansion: A Loop Transformation for Reconfigurable Systems. - Zubair Nawaz; Ozana Silvia Dragomir; Thomas Marconi; Elena Moscu Panainte; Koen Bertels; Stamatis Vassiliadis (FPT, 2007)

Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices. - Thomas Marconi; Yi Lu 004; Koen Bertels; Georgi Gaydadjiev (ARC, 2008)

An efficient algorithm for free resources management on the FPGA. - Yi Lu 004; Thomas Marconi; Georgi Gaydadjiev; Koen Bertels (DATE, 2008)

Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems. - Thomas Marconi; Yi Lu 004; Koen Bertels; Georgi Gaydadjiev (DATE, 2008)

A self-adaptive on-line task placement algorithm for partially reconfigurable systems. - Yi Lu 004; Thomas Marconi; Georgi Gaydadjiev; Koen Bertels; Roel Meeuws (IPDPS, 2008)

Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems. - Yi Lu 004; Thomas Marconi; Koen Bertels; Georgi Gaydadjiev (ARC, 2009)

Flexible pipelining design for recursive variable expansion. - Zubair Nawaz; Thomas Marconi; Koen Bertels; Todor P. Stefanov (IPDPS, 2009)

3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices. - Thomas Marconi; Yi Lu 004; Koen Bertels; Georgi Gaydadjiev (ARC, 2010)

A Communication Aware Online Task Scheduling Algorithm for FPGA-Based Partially Reconfigurable Systems. - Yi Lu 004; Thomas Marconi; Koen Bertels; Georgi Gaydadjiev (FCCM, 2010)

A novel HDL coding style to reduce power consumption for reconfigurable devices. - Thomas Marconi; Dimitris Theodoropoulos; Koen Bertels; Georgi Gaydadjiev (FPT, 2010)

A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices. - Thomas Marconi; Jae Young Hur; Koen Bertels; Georgi Gaydadjiev (SASP, 2010)

A novel online hardware task scheduling and placement algorithm for 3D partially reconfigurable FPGAs. - Thomas Marconi; Tulika Mitra (FPT, 2011)

Efficient Runtime Management of Reconfigurable Hardware Resources. - Thomas Marconi (2011)

Online scheduling for multi-core shared reconfigurable fabric. - Liang Chen; Thomas Marconi; Tulika Mitra (DATE, 2012)

Implementation of core coalition on FPGAs. - Kaushik Triyambaka Mysur; Mihai Pricopi; Thomas Marconi; Tulika Mitra (VLSI-SoC, 2013)

Towards energy effective LDPC decoding by exploiting channel noise variability. - Thomas Marconi; Christian Spagnol; Emanuel M. Popovici; Sorin Cotofana (VLSI-SoC, 2014)

Transmission Channel Noise Aware Energy Effective LDPC Decoding. - Thomas Marconi; Christian Spagnol; Emanuel M. Popovici; Sorin Cotofana (VLSI-SoC (Selected Papers), 2014)

Online scheduling and placement of hardware tasks with multiple variants on dynamically reconfigurable field-programmable gate arrays. - Thomas Marconi (Comput. Electr. Eng., 2014)

Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding. - Thomas Marconi; Sorin Cotofana (ACM Great Lakes Symposium on VLSI, 2015)

LDPC-Based Adaptive Multi-Error Correction for 3D Memories. - Mihai Lefter; George Razvan Voicu; Thomas Marconi; Valentin Savin; Sorin Dan Cotofana (ICCD, 2017)

Low cost multi-error correction for 3D polyhedral memories. - Mihai Lefter; Thomas Marconi; George Razvan Voicu; Sorin Dan Cotofana (NANOARCH, 2017)