High speed digital transceivers: A challenge for manufacturing. - Clifford B. Cole; Thomas P. Warwick (ITC, 1999)

An accurate simulation model of the ATE test environment for very high speed devices. - Thomas P. Warwick; Jung Cho; Yi Cai; Bill Ortner (ITC, 1999)

What a Device Interface Board Really Costs: An Evaluation of Technical Considerations for Testing Products Operating in the Gigabit Region. - Thomas P. Warwick (ITC, 2002)

Mitigating the Effects of The DUT Interface board and Test System Parasitics in Gigabit-Plus Measurements. - Thomas P. Warwick (ITC, 2003)

Measurement Repeatability for RF Test Within the Load-board Constraints of High Density and Fine Pitch SOC Applications. - Thomas P. Warwick; Gustavo Rivera; David Waite; James Russell; Jeffrey Smith (ITC, 2008)