S/390 Parallel Enterprise Server Generation 3: A balanced system and cache structure. - Gerhard Döttling; Klaus Joerg Getzlaff; Bernd Leppla; Walter Lipponer; Thomas Pflueger; Thomas Schlipf; Dietmar Schmunkamp; Udo Wille (IBM J. Res. Dev., 1997)

Standard-cell-based design methodology for high-performance support chips. - Bernhard Kick; Ulrich Baur; Jürgen Koehl; Thomas Ludwig 004; Thomas Pflueger (IBM J. Res. Dev., 1997)

A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset. - Jürgen Koehl; Ulrich Baur; Thomas Ludwig 004; Bernhard Kick; Thomas Pflueger (DATE, 1998)

A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features. - Norman J. Rohrer; Cédric Lichtenau; Peter A. Sandon; Paul Kartschoke; Erwin B. Cohen; Miles G. Canada; Thomas Pflüger; Mathew I. Ringler; Rolf B. Hilgendorf; Stephen F. Geissler; Jeffrey S. Zimmerman (IEEE J. Solid State Circuits, 2005)

A 64B CPU Pair: Dual- and Single-Processor Chips. - Erwin B. Cohen; Norman J. Rohrer; Peter A. Sandon; Miles G. Canada; Cédric Lichtenau; Mathew I. Ringler; Paul Kartschoke; Robert Floyd 002; Jan Heaslip; M. Ross; Thomas Pflueger; Rolf B. Hilgendorf; et al. (ISSCC, 2006)

Scalable and modular pervasive logic/firmware design. - Tobias Webel; Thomas Pflueger; Ralf Ludewig; Cédric Lichtenau; Walter Niklaus; Ralf Schaufler (IBM J. Res. Dev., 2012)

Advanced features in IBM POWER8 systems. - Balaram Sinharoy; Randal C. Swanberg; Naresh Nayar; Bruce G. Mealey; Jeffrey Stuecheli; Berni Schiefer; Jens Leenstra; Joefon Jann; P. Oehler; D. Levitan; S. Eisen; D. Sanner; et al. (IBM J. Res. Dev., 2015)

Editorial. - Thomas Pflüger (Zeitschrift für Bibliothekswesen und Bibliographie (ZfBB), 2023)