A Metastability-Free Multi-synchronous Communication Scheme for SoCs. - Thomas Polzer; Thomas Handl; Andreas Steininger (SSS, 2009)

A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding. - Jakob Lechner; Martin Lampacher; Thomas Polzer (ACSD, 2012)

Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. - Varadan Savulimedu Veeravalli; Thomas Polzer; Andreas Steininger; Ulrich Schmid 001 (DSD, 2012)

Muller C-Element Metastability Containment. - Thomas Polzer; Andreas Steininger; Jakob Lechner (PATMOS, 2012)

An Approach for Efficient Metastability Characterization of FPGAs through the Designer. - Thomas Polzer; Andreas Steininger (ASYNC, 2013)

Digital Late-Transition Metastability Simulation Model. - Thomas Polzer; Andreas Steininger (DSD, 2013)

SET propagation in micropipelines. - Thomas Polzer; Andreas Steininger (PATMOS, 2013)

Metastability characterization for muller C-elements. - Thomas Polzer; Andreas Steininger (PATMOS, 2013)

An infrastructure for accurate characterization of single-event transients in digital circuits. - Varadan Savulimedu Veeravalli; Thomas Polzer; Ulrich Schmid 001; Andreas Steininger; Michael Hofbauer; Kurt Schweiger; Horst Dietrich; Kerstin Schneider-Hornstein; Horst Zimmermann; Kay-Obbe Voss; Bruno Merk; Michael Hajek (Microprocess. Microsystems, 2013)

Containment of Metastable Voltages in FPGAs. - Robert Najvirt; Thomas Polzer; Florian Beck; Andreas Steininger (DDECS, 2015)

Measuring the Distribution of Metastable Upsets over Time. - Thomas Polzer; Andreas Steininger (DSD, 2015)

Enhanced Metastability Characterization Based on AC Analysis. - Thomas Polzer; Andreas Steininger (DSD, 2015)

A general approach for comparing metastable behavior of digital CMOS gates. - Thomas Polzer; Andreas Steininger (DDECS, 2016)

On the Appropriate Handling of Metastable Voltages in FPGAs. - Thomas Polzer; Robert Najvirt; Florian Beck; Andreas Steininger (J. Circuits Syst. Comput., 2016)

Metastability-Aware Memory-Efficient Time-to-Digital Converters. - Matthias Függer; Attila Kinali; Christoph Lenzen 001; Thomas Polzer (ASYNC, 2017)

Measuring Metastability with Free-Running Clocks. - Robert Najvirt; Thomas Polzer; Andreas Steininger (ASYNC, 2017)

Measuring metastability using a time-to-digital converter. - Thomas Polzer; Florian Huemer; Andreas Steininger (DDECS, 2017)

A Model for the Metastability Delay of Sequential Elements. - Thomas Polzer; Andreas Steininger (J. Circuits Syst. Comput., 2017)

Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. - Florian Huemer; Thomas Polzer; Andreas Steininger (DDECS, 2018)

Refined metastability characterization using a time-to-digital converter. - Thomas Polzer; Florian Huemer; Andreas Steininger (Microelectron. Reliab., 2018)

An Experimental Study of Metastability-Induced Glitching Behavior. - Thomas Polzer; Florian Huemer; Andreas Steininger (J. Circuits Syst. Comput., 2019)

Automated Evaluation System for Microcontroller Assignments. - Fabian Steiner; Bernhard Lueger; Bernhard Wallisch; Thomas Polzer (EDUCON, 2023)