RISC-V V Vector Extension (RVV) with reduced number of vector registers. - Eino Jacobs; Dmitry Utyansky; Muhammad Hassan; Thomas Roecker (CoRR, 2024)

RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective. - Sandro Pinto 001; José Martins; Manuel Rodriguez; Luís Cunha; Georg Schmalz; Uwe Moslehner; Kai Dieffenbach; Thomas Roecker (CoRR, 2024)

Virtual memory for real-time systems using hPMP. - Konrad Walluszik; Daniel Auge; Gerhard Wirrer; Holm Rauchfuss; Thomas Roecker (CoRR, 2025)