Yield-Reliability Modeling for Fault Tolerant Integrated Circuits. - Thomas S. Barnett; Adit D. Singh; Victor P. Nelson (DFT, 2001)

Estimating burn-in fall-out for redundant memory. - Thomas S. Barnett; Adit D. Singh; Victor P. Nelson (ITC, 2001)

Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model. - Thomas S. Barnett; Adit D. Singh; Victor P. Nelson (VTS, 2001)

Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model. - Thomas S. Barnett; Matt Grady; Kathleen G. Purdy; Adit D. Singh (ITC, 2002)

Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction. - Thomas S. Barnett; Adit D. Singh; Matt Grady; Kathleen G. Purdy (VTS, 2002)

Relating Yield Models to Burn-In Fall-Out in Time. - Thomas S. Barnett; Adit D. Singh (ITC, 2003)

Extending integrated-circuit yield-models to estimate early-life reliability. - Thomas S. Barnett; Adit D. Singh; Victor P. Nelson (IEEE Trans. Reliab., 2003)

Combining Negative Binomial and Weibull Distributions for Yield and Reliability Prediction. - Thomas S. Barnett; Matt Grady; Kathleen G. Purdy; Adit D. Singh (IEEE Des. Test Comput., 2006)