Switched capacitor DC-DC converter in 65nm CMOS technology with a peak efficiency of 97%. - Thomas Santa; Mario Auer; Christoph Sandner; Christian Lindholm (ISCAS, 2011)

A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider. - Roberto Nonis; Werner Grollitsch; Thomas Santa; Dmytro Cherniak; Nicola Da Dalt (ISSCC, 2013)

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture. - Roberto Nonis; Werner Grollitsch; Thomas Santa; Dmytro Cherniak; Nicola Da Dalt (IEEE J. Solid State Circuits, 2013)