Memory Models for the Formal Verification of Assembler Code Using Bounded Model Checking. - Wolfgang Ecker; Volkan Esen; Thomas Steininger; Martin Zambaldi (ISORC, 2004)

Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach. - Jens Bieger; Sorin A. Huss; Michael Jung 002; Stephan Klaus; Thomas Steininger (VLSI Design, 2004)

Case Study on Transaction Level Modeling. - Wolfgang Ecker; Volkan Esen; Thomas Steininger; Michael Velten (FDL, 2006)

IP Library For Temporal SystemC Assertions. - Wolfgang Ecker; Volkan Esen; Thomas Steininger; Michael Velten; Jacob Smit (FDL, 2006)

Specification Language for Transaction Level Assertions. - Wolfgang Ecker; Volkan Esen; Thomas Steininger; Michael Velten; Michael Hull (HLDVT, 2006)

Requirements and Concepts for Transaction Level Assertions. - Wolfgang Ecker; Volkan Esen; Michael Hull; Thomas Steininger; Michael Velten (ICCD, 2006)

Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. - Wolfgang Ecker; Volkan Esen; Lars Schönberg; Thomas Steininger; Michael Velten; Michael Hull (DATE, 2007)

Interactive presentation: Implementation of a transaction level assertion framework in SystemC. - Wolfgang Ecker; Volkan Esen; Thomas Steininger; Michael Velten; Michael Hull (DATE, 2007)

Requirements and Concepts for Transaction Level Assertion Refinement. - Wolfgang Ecker; Volkan Esen; Thomas Steininger; Michael Velten (IESS, 2007)

Automated assertion transformation across multiple abstraction levels. - Thomas Steininger (2009)

TLM+ modeling of embedded HW/SW systems. - Wolfgang Ecker; Volkan Esen; Robert Schwencker; Thomas Steininger; Michael Velten (DATE, 2010)

Model reduction techniques for the formal verification of hardware dependent software. - Wolfgang Ecker; Volkan Esen; Rainer Findenig; Thomas Steininger; Michael Velten (HLDVT, 2010)