An innovative low-power high-performance programmable signal processor for digital communications. - Jaime H. Moreno; Victor V. Zyuban; Uzi Shvadron; Fredy D. Neeser; Jeff H. Derby; Malcolm S. Ware; Krishnan Kailas; Ayal Zaks; Amir B. Geva; Shay Ben-David; Sameh W. Asaad; Thomas W. Fox; et al. (IBM J. Res. Dev., 2003)

Design methodology for semi custom processor cores. - Victor V. Zyuban; Sameh W. Asaad; Thomas W. Fox; Anne-Marie Haen; Daniel Littrell; Jaime H. Moreno (ACM Great Lakes Symposium on VLSI, 2004)

A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. - Gary S. Ditlow; Robert K. Montoye; Salvatore N. Storino; Sherman M. Dance; Sebastian Ehrenreich; Bruce M. Fleischer; Thomas W. Fox; Kyle M. Holmes; Junichi Mihara; Yutaka Nakamura; Shohji Onishi; Robert Shearer; et al. (ISSCC, 2011)

The IBM Blue Gene/Q Compute Chip. - Ruud A. Haring; Martin Ohmacht; Thomas W. Fox; Michael Gschwind; David L. Satterfield; Krishnan Sugavanam; Paul Coteus; Philip Heidelberger; Matthias A. Blumrich; Robert W. Wisniewski; Alan Gara; George L.-T. Chiu; et al. (IEEE Micro, 2012)

Active Memory Cube: A processing-in-memory architecture for exascale systems. - Ravi Nair; Samuel Antão; Carlo Bertolli; Pradip Bose; José R. Brunheroto; Tong Chen 001; Chen-Yong Cher; Carlos H. A. Costa; J. Doi; Constantinos Evangelinos; Bruce M. Fleischer; Thomas W. Fox; et al. (IBM J. Res. Dev., 2015)

Across the Stack Opportunities for Deep Learning Acceleration. - Vijayalakshmi Srinivasan; Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (ISLPED, 2018)

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. - Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Vijayalakshmi Srinivasan; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (VLSI Circuits, 2018)

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. - Jinwook Oh; Sae Kyu Lee; Mingu Kang; Matthew M. Ziegler; Joel Silberman; Ankur Agrawal; Swagath Venkataramani; Bruce M. Fleischer; Michael Guillorn; Jungwook Choi; Wei Wang 333; Silvia M. Mueller; et al. (VLSI Circuits, 2020)

Efficient AI System Design With Cross-Layer Approximate Computing. - Swagath Venkataramani; Xiao Sun 013; Naigang Wang; Chia-Yu Chen; Jungwook Choi; Mingu Kang; Ankur Agarwal; Jinwook Oh; Shubham Jain; Tina Babinsky; Nianzheng Cao; Thomas W. Fox; et al. (Proc. IEEE, 2020)