Effect of Record Length on Noise-Induced Error in the Cross Correlation Estimate. - Daniel J. Krause; John W. Steadman; Thomas W. Williams (IEEE Trans. Syst. Man Cybern., 1972)

A logic design structure for LSI testability. - Edward B. Eichelberger; Thomas W. Williams (DAC, 1977)

Testing Logic Networks and Designing for Testability. - Thomas W. Williams; Kenneth P. Parker (Computer, 1979)

Design for testability. - Thomas W. Williams (DAC, 1982)

A Variation of LSSD and Its Implications on Design and Test Pattern Generation in VLSI. - Sumit DasGupta; Prabhakar Goel; Ron G. Walther; Tom W. Williams (ITC, 1982)

Analysis of the Switching Behavior of Combinatorial Logic Networks. - Eugen I. Muehldorf; Thomas W. Williams (ITC, 1982)

Design for Testability - A Survey. - Thomas W. Williams; Kenneth P. Parker (IEEE Trans. Computers, 1982)

Chip partitioning aid: A design technique for partitionability and testability in VLSI. - Subrata Dasgupta; M. C. Graf; Robert A. Rasmussen; Ron G. Walther; Tom W. Williams (DAC, 1984)

Sufficient Testing In A Self-Testing Environment. - Tom W. Williams (ITC, 1984)

VLSI Testing. - Thomas W. Williams (Computer, 1984)

Test Length in a Self-Testing Environment. - Thomas W. Williams (IEEE Des. Test, 1985)

Comparison of Aliasing Errors for Primitive and Non-Primitive Polynomials. - Tom W. Williams; Wilfried Daehn; Matthias Gruetzner; Corot W. Starke (ITC, 1986)

Design of testable logic circuits. - Thomas W. Williams (Proc. IEEE, 1986)

Aliasing Errors in Signature Analysis Registers. - Tom W. Williams; Wilfried Daehn; Matthias Gruetzner; Corot W. Starke (IEEE Des. Test, 1987)

Statistical Delay Fault Coverage and Defect Level for Delay Faults. - Eun Sei Park; Thomas W. Williams; M. Ray Mercer (ITC, 1988)

Design for Testability of Mixed Signal Integrated Circuits. - Kenneth D. Wagner; Thomas W. Williams (ITC, 1988)

TRIM: testability range by ignoring the memory. - Larry Carter; Leendert M. Huisman; Tom W. Williams (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Bounds and analysis of aliasing errors in linear feedback shift registers. - Tom W. Williams; Wilfried Daehn; Matthias Gruetzner; Corot W. Starke (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Future Trends in the Testing. - Thomas W. Williams (IFIP Congress, 1989)

A statistical model for delay-fault testing. - Eun Sei Park; M. Ray Mercer; Thomas W. Williams (IEEE Des. Test, 1989)

The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. - Thomas W. Williams; Bill Underwood; M. Ray Mercer (DAC, 1991)

Delay Testing Quality in Timing-Optimized Designs. - Eun Sei Park; Bill Underwood; Thomas W. Williams; M. Ray Mercer (ITC, 1991)

Enhancing Board Functional Self-Test by Concurrent Sampling. - Kenneth D. Wagner; Thomas W. Williams (ITC, 1991)

Iterative algorithms for computing aliasing probabilities. - André Ivanov; Corot W. Starke; Vinod K. Agarwal; Wilfried Daehn; Matthias Gruetzner; Tom W. Williams (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

The Total Delay Fault Model and Statistical Delay Fault Coverage. - Eun Sei Park; M. Ray Mercer; Thomas W. Williams (IEEE Trans. Computers, 1992)

Design for Testability: Today and in the Future. - Thomas W. Williams (ICCD, 1993)

Fault Modeling and Defect Level Projections in Digital ICs. - José T. de Sousa; Fernando M. Gonçalves; João Paulo Teixeira 001; Thomas W. Williams (EDAC-ETC-EUROASIC, 1994)

Design of an Efficient Weighted-Random-Pattern Generation System. - Rohit Kapur; Srinivas Patil; Thomas J. Snethen; Thomas W. Williams (ITC, 1994)

Limitations in predicting defect level based on stuck-at fault coverage. - Jaehong Park; Mark Naivar; Rohit Kapur; M. Ray Mercer; Thomas W. Williams (VTS, 1994)

Enhanced testing performance via unbiased test sets. - Li-C. Wang; M. Ray Mercer; Thomas W. Williams (ED&TC, 1995)

On Efficiently and Reliably Achieving Low Defective Part Levels. - Li-C. Wang; M. Ray Mercer; Thomas W. Williams (ITC, 1995)

On the decline of testing efficiency as fault coverage approaches 100%. - Li-C. Wang; M. Ray Mercer; Sophia W. Kao; Thomas W. Williams (VTS, 1995)

Iddq Testing for High Performance CMOS - The Next Ten Years. - Thomas W. Williams; Rohit Kapur; M. Ray Mercer; Robert H. Dennard; Wojciech Maly (ED&TC, 1996)

A Better ATPG Algorithm and Its Design Principles. - Li-C. Wang; M. Ray Mercer; Thomas W. Williams (ICCD, 1996)

Using Target Faults To Detect Non-Tartget Defects. - Li-C. Wang; M. Ray Mercer; Thomas W. Williams (ITC, 1996)

IDDQ Test: Sensitivity Analysis of Scaling. - Thomas W. Williams; Robert H. Dennard; Rohit Kapur; M. Ray Mercer; Wojciech Maly (ITC, 1996)

A weighted random pattern test generation system. - Rohit Kapur; Srinivas Patil; Thomas J. Snethen; Thomas W. Williams (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Defect level evaluation in an IC design environment. - José T. de Sousa; Fernando M. Gonçalves; João Paulo Teixeira 001; Cristoforo Marzocca; Francesco Corsi; Thomas W. Williams (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

The New Frontier for Testing: Nano Meter Technologies. - Thomas W. Williams (Asian Test Symposium, 1998)

Testing in Nanometer Technologies. - Thomas W. Williams (DATE, 1999)

Tough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction. - Rohit Kapur; Thomas W. Williams (Computer, 1999)

IEEE-USA and the Issue of Member Choice. - Thomas W. Williams (Computer, 1999)

DFT closure. - Farhad Hayat; Thomas W. Williams; Rohit Kapur; D. Hsu (Asian Test Symposium, 2000)

Design for Testability in Nanometer Technologies; Searching for Quality. - Thomas W. Williams; Rohit Kapur (ISQED, 2000)

How Should Fault Coverage Be Defined? - Thomas W. Williams; Stephen K. Sunter (VTS, 2000)

The Mutating Metric for Benchmarking Test. - Rohit Kapur; Cy Hay; Thomas W. Williams (IEEE Des. Test Comput., 2000)

An industrial view of electronic design automation. - Don MacMillen; Raul Camposano; Dwight D. Hill; Thomas W. Williams (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Tester retargetable patterns. - Rohit Kapur; Thomas W. Williams (ITC, 2001)

A new methodology for improved tester utilization. - Ajay Khoche; Rohit Kapur; David Armstrong; Thomas W. Williams; Mick Tegethoff; Jochen Rivoir (ITC, 2001)

Design of compactors for signature-analyzers in built-in self-test. - Peter Wohl; John A. Waicukauski; Thomas W. Williams (ITC, 2001)

Strategies for Low-Cost Test. - Rohit Kapur; R. Chandramouli; Thomas W. Williams (IEEE Des. Test Comput., 2001)

Manufacturing Test of SoCs. - Rohit Kapur; Thomas W. Williams (Asian Test Symposium, 2002)

Enhancing test efficiency for delay fault testing using multiple-clocked schemes. - Jing-Jia Liou; Li-C. Wang; Kwang-Ting Cheng; Jennifer Dworak; M. Ray Mercer; Rohit Kapur; Thomas W. Williams (DAC, 2002)

Directed-Binary Search in Logic BIST Diagnostics. - Rohit Kapur; Thomas W. Williams; M. Ray Mercer (DATE, 2002)

Fast seed computation for reseeding shift register in test pattern compression. - Nahmsuk Oh; Rohit Kapur; Thomas W. Williams (ICCAD, 2002)

Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. - Jing-Jia Liou; Li-C. Wang; Kwang-Ting Cheng; Jennifer Dworak; M. Ray Mercer; Rohit Kapur; Thomas W. Williams (ITC, 2002)

Dynamic Scan: Driving Down the Cost of Test. - Samitha Samaranayake; Nodari Sitchinava; Rohit Kapur; Minesh B. Amin; Thomas W. Williams (Computer, 2002)

Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture. - Nahmsuk Oh; Rohit Kapur; Thomas W. Williams; Jim Sproch (DATE, 2003)

Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. - Li-C. Wang; Angela Krstic; Leonard Lee; Kwang-Ting Cheng; M. Ray Mercer; Thomas W. Williams; Magdy S. Abadir (ITC, 2003)

A Reconfigurable Shared Scan-in Architecture. - Samitha Samaranayake; Emil Gizdarski; Nodari Sitchinava; Frederic Neuveux; Rohit Kapur; Thomas W. Williams (VTS, 2003)

Changing the Scan Enable during Shift. - Nodari Sitchinava; Samitha Samaranayake; Rohit Kapur; Emil Gizdarski; Frederic Neuveux; Thomas W. Williams (VTS, 2004)

Design for Testability: The Path to Deep Submicron. - Thomas W. Williams (Asian Test Symposium, 2005)

Efficient compression of deterministic patterns into multiple PRPG seeds. - Peter Wohl; John A. Waicukauski; Sanjay Patel; Francisco DaSilva; Thomas W. Williams; Rohit Kapur (ITC, 2005)

TTTC recognizes test visionary's lifetime contribution. - Thomas W. Williams (IEEE Des. Test Comput., 2005)

Accurately Determining Bridging Defects from Layout. - Maria Gkatziani; Rohit Kapur; Qing Su; Ben Mathew; Roberto Mattiuzzo; Laura Tarantini; Cy Hay; Salvatore Talluto 001; Thomas W. Williams (DDECS, 2007)

EDA to the Rescue of the Silicon Roadmap. - Thomas W. Williams (ISQED, 2007)

Fundamentals of timing information for test: How simple can we get? - Rohit Kapur; Jindrich Zejda; Thomas W. Williams (ITC, 2007)

Minimizing the Impact of Scan Compression. - Peter Wohl; John A. Waicukauski; Rohit Kapur; Sanjay Ramnath; Emil Gizdarski; Thomas W. Williams; P. Jaini (VTS, 2007)

DFT MAX and Power. - Rohit Kapur; T. Finklea; Felix Ng; Anshuman Chandra; Sanjay Ramnath; Peter Wohl; Thomas W. Williams; Ashok Anbalan; Sandeep S. Kulkarni; Tammy Fernandes; Pramod Notiyath; Rajesh Uppuluri (J. Low Power Electron., 2007)

Reaching the limits of low power design. - J. S. Hobbs; Thomas W. Williams (ASP-DAC, 2008)

Evaluation of Entropy Driven Compression Bounds on Industrial Designs. - Srinivasulu Alampally; Jais Abraham; Rubin A. Parekhji; Rohit Kapur; Thomas W. Williams (ATS, 2008)

The Future Is Low Power and Test. - Thomas W. Williams (ETS, 2008)

Historical Perspective on Scan Compression. - Rohit Kapur; Subhasish Mitra; Thomas W. Williams (IEEE Des. Test Comput., 2008)