Self-Adaptive Parallel Processing Architecture For High-speed Networking. - Jürgen Foag; Nuria Pazos; Thomas Wild; Winthir Brunnbauer (HPCS, 2002)

Predictive methodology for high-performance networking. - Jürgen Foag; Thomas Wild; Nuria Pazos; Winthir Brunnbauer (ISCC, 2002)

A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges. - Winthir Brunnbauer; Thomas Wild; Jürgen Foag; Nuria Pazos (DSD, 2003)

Mapping and Scheduling for Architecture Exploration of Networking SoCs. - Thomas Wild; Jürgen Foag; Nuria Pazos; Winthir Brunnbauer (VLSI Design, 2003)

Ein rekursives Verfahren zur Abbildung und zum Scheduling von Prozess-Graphen mit Kontrollabhängigkeiten. - Thomas Wild (2003)

FlexPath NP: a network processor concept with application-driven flexible processing paths. - Rainer Ohlendorf; Andreas Herkersdorf; Thomas Wild (CODES+ISSS, 2005)

Predictive processing architecture extension for network processors. - Jürgen Foag; Thomas Wild (ICECS, 2005)

TAPES - Trace-based architecture performance evaluation with SystemC. - Thomas Wild; Andreas Herkersdorf; Gyoo-Yeong Lee (Des. Autom. Embed. Syst., 2005)

Reconfigurable Processing Units vs. Reconfigurable Interconnects. - Andreas Herkersdorf; Christopher Claus; Michael Meitinger; Rainer Ohlendorf; Thomas Wild (Dynamically Reconfigurable Architectures, 2006)

Performance evaluation for system-on-chip architectures using trace-based transaction level simulation. - Thomas Wild; Andreas Herkersdorf; Rainer Ohlendorf (DATE, 2006)

Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications. - Rainer Ohlendorf; Thomas Wild; Michael Meitinger; Holm Rauchfuss; Andreas Herkersdorf (ICSAMOS, 2006)

Queuing algorithm for speculative Network Processors. - Jürgen Foag; Thomas Wild (Int. J. High Perform. Comput. Netw., 2006)

Power Estimation of Time Variant SoCs with TAPES. - Andreas Lankes; Thomas Wild; Johannes Zeppenfeld (DSD, 2007)

A Programmable Stream Processing Engine for Packet Manipulation in Network Processors. - Michael Meitinger; Rainer Ohlendorf; Thomas Wild; Andreas Herkersdorf (ISVLSI, 2007)

Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications. - Rainer Ohlendorf; Thomas Wild; Michael Meitinger; Holm Rauchfuss; Andreas Herkersdorf (J. Syst. Archit., 2007)

System Level Simulation of Autonomic SoCs with TAPES. - Andreas Lankes; Thomas Wild; Johannes Zeppenfeld (ARCS, 2008)

A Hardware Packet Re-Sequencer Unit for Network Processors. - Michael Meitinger; Rainer Ohlendorf; Thomas Wild; Andreas Herkersdorf (ARCS, 2008)

Buffer allocation for advanced packet segmentation in Network Processors. - Daniel Llorente; Kimon Karras; Thomas Wild; Andreas Herkersdorf (ASAP, 2008)

Network processors. - Thilo Pionteck; Roman Koch; Carsten Albrecht; Erik Maehle; Michael Meitinger; Rainer Ohlendorf; Thomas Wild; Andreas Herkersdorf (FPL, 2008)

FlexPath NP - A network processor architecture with flexible processing paths. - Michael Meitinger; Rainer Ohlendorf; Thomas Wild; Andreas Herkersdorf (SoC, 2008)

Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor Design. - Zhonglei Wang; Thomas Wild; Stefan Rüping; Bernhard Lippmann (ISVLSI, 2008)

Improving memory subsystem performance in network processors with smart packet segmentation. - Kimon Karras; Daniel Llorente; Thomas Wild; Andreas Herkersdorf (ICSAMOS, 2008)

A Processing Path Dispatcher in Network Processor MPSoCs. - Rainer Ohlendorf; Michael Meitinger; Thomas Wild; Andreas Herkersdorf (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources. - Andreas Lankes; Thomas Wild; Andreas Herkersdorf (DSD, 2009)

FlexPath NP - Flexible, Dynamically Reconfigurable Processing Paths in Network Processors. - Rainer Ohlendorf; Michael Meitinger; Thomas Wild; Andreas Herkersdorf (Dynamically Reconfigurable Systems, 2010)

A folded pipeline network processor architecture for 100 Gbit/s networks. - Kimon Karras; Thomas Wild; Andreas Herkersdorf (ANCS, 2010)

An Application-Aware Load Balancing Strategy for Network Processors. - Rainer Ohlendorf; Michael Meitinger; Thomas Wild; Andreas Herkersdorf (HiPEAC, 2010)

Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks. - Andreas Lankes; Thomas Wild; Andreas Herkersdorf; Sören Sonntag; Helmut Reinig (NOCS, 2010)

Hardware Support for Efficient Resource Utilization in Manycore Processor Systems. - Andreas Herkersdorf; Andreas Lankes; Michael Meitinger; Rainer Ohlendorf; Stefan Wallentowitz; Thomas Wild; Johannes Zeppenfeld (Multiprocessor System-on-Chip, 2011)

Accelerating collective communication in message passing on manycore System-on-Chip. - Stefan Wallentowitz; Marcel Meyer; Thomas Wild; Andreas Herkersdorf (ICSAMOS, 2011)

Advanced Packet Segmentation and Buffering Algorithms in Network Processors. - Daniel Llorente; Kimon Karras; Thomas Wild; Andreas Herkersdorf (Trans. High Perform. Embed. Archit. Compil., 2011)

Enhanced Reliability in Tiled Manycore Architectures through Transparent Task Relocation. - Holm Rauchfuss; Thomas Wild; Andreas Herkersdorf (ARCS Workshops, 2012)

Invasive manycore architectures. - Jörg Henkel; Andreas Herkersdorf; Lars Bauer; Thomas Wild; Michael Hübner 001; Ravi Kumar Pujari; Artjom Grudnitsky; Jan Heisswolf; Aurang Zaib; Benjamin Vogel; Vahid Lari; Sebastian Kobbe (ASP-DAC, 2012)

TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs. - Felix Miller; Thomas Wild; Andreas Herkersdorf (DSD, 2012)

An integrated simulation framework for invasive computing. - Michael Gerndt; Frank Hannig; Andreas Herkersdorf; Andreas Hollmann; Marcel Meyer; Sascha Roloff; Josef Weidendorfer; Thomas Wild; Aurang Zaib (FDL, 2012)

A framework for Open Tiled Manycore System-On-Chip. - Stefan Wallentowitz; Andreas Lankes; Aurang Zaib; Thomas Wild; Andreas Herkersdorf (FPL, 2012)

Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS. - Jan Heisswolf; Aurang Zaib; Andreas Weichslgartner; Ralf König 001; Thomas Wild; Jürgen Teich; Andreas Herkersdorf; Jürgen Becker 001 (IPDPS Workshops, 2012)

System-level software performance simulation considering out-of-order processor execution. - Roman Plyaskin; Thomas Wild; Andreas Herkersdorf (ISSoC, 2012)

Multicore Enablement for Automotive Cyber Physical Systems. - Andreas Herkersdorf; Hans-Ulrich Michel; Holm Rauchfuss; Thomas Wild (it Inf. Technol., 2012)

Benefits of selective packet discard in networks-on-chip. - Andreas Lankes; Thomas Wild; Stefan Wallentowitz; Andreas Herkersdorf (ACM Trans. Archit. Code Optim., 2012)

HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation. - Stefan Wallentowitz; Thomas Wild; Andreas Herkersdorf (ARCS, 2013)

New Algorithm for Analysis of Off-target Effects in siRNA Screens. - Karol Kozak; Sandra Kaestner; Thomas Wild; Andreas Vonderheit; Benjamin Misselwitz; Ulrike Kutay; Gabor Csucs (BIOINFORMATICS, 2013)

AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections. - Aurang Zaib; Jan Heisswolf; Andreas Weichslgartner; Thomas Wild; Jürgen Teich; Jürgen Becker 001; Andreas Herkersdorf (DSD, 2013)

Potentials and Challenges for Multi-Core Processors in Robotic Applications. - Andreas Herkersdorf; Johny Paul; Ravi Kumar Pujari; Walter Stechele; Stefan Wallentowitz; Thomas Wild; Aurang Zaib (GI-Jahrestagung, 2013)

Hardware Supported Adaptive Data Collection for Networks on Chip. - Jan Heisswolf; Andreas Weichslgartner; Aurang Zaib; Ralf König 001; Thomas Wild; Andreas Herkersdorf; Jürgen Teich; Jürgen Becker 001 (IPDPS Workshops, 2013)

Open Tiled Manycore System-on-Chip - Stefan Wallentowitz; Philipp Wagner 001; Michael Tempelmeier; Thomas Wild; Andreas Herkersdorf (CoRR, 2013)

Virtualized and fault-tolerant inter-layer-links for 3D-ICs. - Felix Miller; Thomas Wild; Andreas Herkersdorf (Microprocess. Microsystems, 2013)

Virtual networks - distributed communication resource management. - Jan Heisswolf; Aurang Zaib; Andreas Weichslgartner; Ralf König 001; Thomas Wild; Jürgen Teich; Andreas Herkersdorf; Jürgen Becker 001 (ACM Trans. Reconfigurable Technol. Syst., 2013)

The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure. - Jan Heisswolf; Aurang Zaib; Andreas Weichslgartner; Martin Karle; Maximilian Singh; Thomas Wild; Jürgen Teich; Andreas Herkersdorf; Jürgen Becker 001 (ARCS Workshops, 2014)

Performance Isolation Exposure in Virtualized Platforms with PCI Passthrough I/O Sharing. - Andre Oliver Richter; Christian Herber; Holm Rauchfuss; Thomas Wild; Andreas Herkersdorf (ARCS, 2014)

System integration - The bridge between More than Moore and More Moore. - Andy Heinig; Manfred Dietrich; Andreas Herkersdorf; Felix Miller; Thomas Wild; Kai Hahn; Armin Grünewald; Rainer Brück 001; Steffen Krohnert; Jochen Reisinger (DATE, 2014)

Dependable task and communication migration in tiled manycore system-on-chip. - Stefan Wallentowitz; Stefan Rosch; Thomas Wild; Andreas Herkersdorf; Volker Wenzel; Jörg Henkel (FDL, 2014)

Deadline-Aware Interrupt Coalescing in Controller Area Network (CAN). - Christian Herber; Andre Oliver Richter; Thomas Wild; Andreas Herkersdorf (HPCC/CSS/ICESS, 2014)

A network virtualization approach for performance isolation in controller area network (CAN). - Christian Herber; Andre Oliver Richter; Thomas Wild; Andreas Herkersdorf (RTAS, 2014)

A Layered Modeling and Simulation Approach to investigate Resource-aware Computing in MPSoCs. - Aurang Zaib; Prashanth Raju; Thomas Wild; Andreas Herkersdorf (CoRR, 2014)

A Hardware/Software Approach for Mitigating Performance Interference Effects in Virtualized Environments Using SR-IOV. - Andre Oliver Richter; Christian Herber; Stefan Wallentowitz; Thomas Wild; Andreas Herkersdorf (CLOUD, 2015)

Fault-tolerant communication in invasive networks on chip. - Jan Heisswolf; Andreas Weichslgartner; Aurang Zaib; Stephanie Friederich; Leonard Masing; Carsten Stein; Marco Duden; Roman Klopfer; Jürgen Teich; Thomas Wild; Andreas Herkersdorf; Jürgen Becker 001 (AHS, 2015)

Network Interface with Task Spawning Support for NoC-Based DSM Architectures. - Aurang Zaib; Jan Heißwolf; Andreas Weichslgartner; Thomas Wild; Jürgen Teich; Jürgen Becker 001; Andreas Herkersdorf (ARCS, 2015)

Real-time capable CAN to AVB ethernet gateway using frame aggregation and scheduling. - Christian Herber; Andre Oliver Richter; Thomas Wild; Andreas Herkersdorf (DATE, 2015)

A hardware-based multi-objective thread mapper for tiled manycore architectures. - Ravi Kumar Pujari; Thomas Wild; Andreas Herkersdorf (ICCD, 2015)

Sharer status-based caching in tiled multiprocessor systems-on-chip. - P. Parayil Mana Damodaran; Aurang Zaib; Stefan Wallentowitz; Thomas Wild; Andreas Herkersdorf (SpringSim (HPS), 2015)

Adaptive multi-layer techniques for increased system dependability. - Lars Bauer; Jörg Henkel; Andreas Herkersdorf; Michael A. Kochte; Johannes Maximilian Kühn; Wolfgang Rosenstiel; Thomas Schweizer; Stefan Wallentowitz; Volker Wenzel; Thomas Wild; Hans-Joachim Wunderlich; Hongyan Zhang 004 (it Inf. Technol., 2015)

Denial-of-Service attacks on PCI passthrough devices: Demonstrating the impact on network- and storage-I/O performance. - Andre Oliver Richter; Christian Herber; Thomas Wild; Andreas Herkersdorf (J. Syst. Archit., 2015)

Estimation of End-to-End Packet Error Rates for NoC Multicasts. - Michael Vonbun; Thomas Wild; Andreas Herkersdorf (ARCS, 2016)

DiaSys: On-Chip Trace Analysis for Multi-processor System-on-Chip. - Philipp Wagner 001; Thomas Wild; Andreas Herkersdorf (ARCS, 2016)

Resolving Performance Interference in SR-IOV Setups with PCIe Quality-of-Service Extensions. - Andre Oliver Richter; Christian Herber; Thomas Wild; Andreas Herkersdorf (DSD, 2016)

What happens on an MPSoC stays on an MPSoC - unfortunately! - Philipp Wagner 001; Lin Li 046; Thomas Wild; Albrecht Mayer; Andreas Herkersdorf (ISIC, 2016)

Hardware acceleration of signature matching through multi-layer transition bit masking. - Subramanian Shiva Shankar; Pinxing Lin; Andreas Herkersdorf; Thomas Wild (ITNAC, 2016)

A Rule-based Methodology for Hardware Configuration Validation in Embedded Systems. - Lin Li 046; Philipp Wagner 001; Ramesh Ramaswamy; Albrecht Mayer; Thomas Wild; Andreas Herkersdorf (SCOPES, 2016)

TCU: A Multi-Objective Hardware Thread Mapping Unit for HPC Clusters. - Ravi Kumar Pujari; Thomas Wild; Andreas Herkersdorf (ISC, 2016)

Improving SoC Insight Through On-Chip Diagnosis. - Philipp Wagner 001; Thomas Wild; Andreas Herkersdorf (CoRR, 2016)

Dark silicon management: an integrated and coordinated cross-layer approach. - Santiago Pagani; Lars Bauer; Qingqing Chen 004; Elisabeth Glocker; Frank Hannig; Andreas Herkersdorf; Heba Khdr; Anuj Pathania; Ulf Schlichtmann; Doris Schmitt-Landsiedel; Mark Sagi; Éricles Sousa; et al. (it Inf. Technol., 2016)

MPSoC application resilience by hardware-assisted communication virtualization. - Stefan Rosch; Holm Rauchfuss; Stefan Wallentowitz; Thomas Wild; Andreas Herkersdorf (Microelectron. Reliab., 2016)

Reducing Data Center Resource Over-Provisioning Through Dynamic Load Management for Virtualized Network Functions. - Andreas Oeldemann; Thomas Wild; Andreas Herkersdorf (ARCS, 2017)

A non-intrusive, operating system independent spinlock profiler for embedded multicore systems. - Lin Li 046; Philipp Wagner 001; Albrecht Mayer; Thomas Wild; Andreas Herkersdorf (DATE, 2017)

Adaptive Reliability for Fault Tolerant Multicore Systems. - Ihsen Alouani; Thomas Wild; Andreas Herkersdorf; Smaïl Niar (DSD, 2017)

A Divide and Conquer State Grouping Method for Bitmap Based Transition Compression. - Subramanian Shiva Shankar; Pinxing Lin; Andreas Herkersdorf; Thomas Wild (PDCAT, 2017)

Region based cache coherence for tiled MPSoCs. - Akshay Srivatsa; Sven Rheindt; Thomas Wild; Andreas Herkersdorf (SoCC, 2017)

DiaSys: Improving SoC insight through on-chip diagnosis. - Philipp Wagner 001; Thomas Wild; Andreas Herkersdorf (J. Syst. Archit., 2017)

Efficient task spawning for shared memory and message passing in many-core architectures. - Aurang Zaib; Thomas Wild; Andreas Herkersdorf; Jan Heisswolf; Jürgen Becker 001; Andreas Weichslgartner; Jürgen Teich (J. Syst. Archit., 2017)

CaCAO: Complex and Compositional Atomic Operations for NoC-Based Manycore Platforms. - Sven Rheindt; Andreas Schenk; Akshay Srivatsa; Thomas Wild; Andreas Herkersdorf (ARCS, 2018)

BiSME: A Hardware Coprocessor to Perform Signature Matching at Multi-Gigabit Rates. - Subramanian Shiva Shankar; Pinxing Lin; Andreas Herkersdorf; Thomas Wild (ASAP, 2018)

Design methodologies for enabling self-awareness in autonomous systems. - Armin Sadighi; Bryan Donyanavard; Thawra Kadeed; Kasra Moazzemi; Tiago Mück; Ahmed Nassar 001; Amir M. Rahmani; Thomas Wild; Nikil D. Dutt; Rolf Ernst; Andreas Herkersdorf; Fadi J. Kurdahi (DATE, 2018)

FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet. - Andreas Oeldemann; Thomas Wild; Andreas Herkersdorf (FPL, 2018)

Memory Access Pattern Profiling for Streaming Applications Based on MATLAB Models. - Thomas Goldbrunner; Thomas Wild; Andreas Herkersdorf (PATMOS, 2018)

Platform-Centric Self-Awareness as a Key Enabler for Controlling Changes in CPS. - Mischa Möstl; Johannes Schlatow; Rolf Ernst; Nikil D. Dutt; Ahmed Nassar 001; Amir-Mohammad Rahmani; Fadi J. Kurdahi; Thomas Wild; Armin Sadighi; Andreas Herkersdorf (Proc. IEEE, 2018)

Cryptographic Hashing in P4 Data Planes. - Dominik Scholz; Andreas Oeldemann; Fabien Geyer; Sebastian Gallenmüller; Henning Stubbe; Thomas Wild; Andreas Herkersdorf; Georg Carle (ANCS, 2019)

A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC. - Max Koenen; Nguyen Anh Vu Doan; Thomas Wild; Andreas Herkersdorf (ARCS, 2019)

Network Coding in Networks-on-Chip with Lossy Links. - Michael Vonbun; Nguyen Anh Vu Doan; Thomas Wild; Andreas Herkersdorf (ARCS, 2019)

The information processing factory: a paradigm for life cycle management of dependable systems. - Eberle A. Rambo; Thawra Kadeed; Rolf Ernst; Minjun Seo; Fadi J. Kurdahi; Bryan Donyanavard; Caio Batista de Melo; Biswadip Maity; Kasra Moazzemi; Kenneth Michael Stewart; Saehanseul Yi; Amir M. Rahmani; et al. (CODES+ISSS, 2019)

Multi-Objective Optimization of Channel Mapping for Fail-Operational Hybrid TDM NoCs. - Nguyen Anh Vu Doan; Max Koenen; Thomas Wild; Andreas Herkersdorf (CANDAR Workshops, 2019)

Multicore Power Estimation using Independent Component Analysis Based Modeling. - Mark Sagi; Nguyen Anh Vu Doan; Thomas Wild; Andreas Herkersdorf (MCSoC, 2019)

NEMESYS: near-memory graph copy enhanced system-software. - Sven Rheindt; Andreas Fried; Oliver Lenke; Lars Nolte; Thomas Wild; Andreas Herkersdorf (MEMSYS, 2019)

Channel mapping strategies for effective protection switching in fail-operational hard real-time NoCs. - Max Koenen; Nguyen Anh Vu Doan; Thomas Wild; Andreas Herkersdorf (NOCS, 2019)

APEC: improved acknowledgement prioritization through erasure coding in bufferless NoCs. - Michael Vonbun; Adrian Schiechel; Nguyen Anh Vu Doan; Thomas Wild; Andreas Herkersdorf (NOCS, 2019)

SHARQ: Software-Defined Hardware-Managed Queues for Tile-Based Manycore Architectures. - Sven Rheindt; Sebastian Maier; Florian Schmaus; Thomas Wild; Wolfgang Schröder-Preikschat; Andreas Herkersdorf (SAMOS, 2019)

CoD: Coherence-on-Demand - Runtime Adaptable Working Set Coherence for DSM-Based Manycore Architectures. - Akshay Srivatsa; Sven Rheindt; Dirk Gabriel; Thomas Wild; Andreas Herkersdorf (SAMOS, 2019)

Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications. - Thomas Goldbrunner; Nguyen Anh Vu Doan; Diogo Poças; Thomas Wild; Andreas Herkersdorf (SoCC, 2019)

X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-Based MPSoCs. - Sven Rheindt; Andreas Fried; Oliver Lenke; Lars Nolte; Temur Sabirov; Tim Twardzik; Thomas Wild; Andreas Herkersdorf (ARCS, 2020)

On-Chip Democracy: A Study on the Use of Voting Systems for Computer Cache Memory Management. - Nguyen Anh Vu Doan; Akshay Srivatsa; Nael Fasfous; Sebastian Nagel 004; Thomas Wild; Andreas Herkersdorf (IEEM, 2020)

X-Centric: A Survey on Compute-, Memory- and Application-Centric Computer Architectures. - Sven Rheindt; Temur Sabirov; Oliver Lenke; Thomas Wild; Andreas Herkersdorf (MEMSYS, 2020)

Exploring Task and Channel Mapping Strategies in Fail-Operational and Hard Real-Time NoCs. - Max Koenen; Nguyen Anh Vu Doan; Thomas Wild; Andreas Herkersdorf (NorCAS, 2020)

HyVE: A Hybrid Voting-based Eviction Policy for Caches. - Akshay Srivatsa; Sebastian Nagel 004; Nael Fasfous; Nguyen Anh Vu Doan; Thomas Wild; Andreas Herkersdorf (NorCAS, 2020)

Inter-Server RSS: Extending Receive Side Scaling for Inter-Server Workload Distribution. - Andreas Oeldemann; Franz Biersack; Thomas Wild; Andreas Herkersdorf (PDP, 2020)

A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power. - Mark Sagi; Nguyen Anh Vu Doan; Martin Rapp; Thomas Wild; Jörg Henkel; Andreas Herkersdorf (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs. - Yong Hu; Marcel Mettler; Daniel Mueller-Gritschneder; Thomas Wild; Andreas Herkersdorf; Ulf Schlichtmann (ACM Trans. Design Autom. Electr. Syst., 2020)

Precise real-time monitoring of time-critical flows. - Kilian Holzinger; Henning Stubbe; Franz Biersack; Angela Gonzalez Mariño; Abdoul Kane; Francisco Fons Lluis; Haigang Zhang; Thomas Wild; Andreas Herkersdorf; Georg Carle (CoNEXT, 2021)

Long Short-Term Memory Neural Network-based Power Forecasting of Multi-Core Processors. - Mark Sagi; Martin Rapp; Heba Khdr; Yizhe Zhang 005; Nael Fasfous; Nguyen Anh Vu Doan; Thomas Wild; Jörg Henkel; Andreas Herkersdorf (DATE, 2021)

PEPERONI: Pre-Estimating the Performance of Near-Memory Integration. - Oliver Lenke; Richard Petri 002; Thomas Wild; Andreas Herkersdorf (MEMSYS, 2021)

DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based Architectures. - Sven Rheindt; Sebastian Maier; Nora Pohle; Lars Nolte; Oliver Lenke; Florian Schmaus; Thomas Wild; Wolfgang Schröder-Preikschat; Andreas Herkersdorf (Int. J. Parallel Program., 2021)

DynaCo: Dynamic Coherence Management for Tiled Manycore Architectures. - Akshay Srivatsa; Mostafa Mansour; Sven Rheindt; Dirk Gabriel; Thomas Wild; Andreas Herkersdorf (Int. J. Parallel Program., 2021)

plutus: An R package to calculate electricity investments and stranded assets from the Global Change Analysis Model (GCAM). - Mengqi Zhao; Matthew Binsted; Thomas Wild; Zarrar Khan; Brinda Yarlagadda; Gokul Iyer; Chris R. Vernon; Pralit Patel; Sílvia da Silva; Katherine V. Calvin (J. Open Source Softw., 2021)

Protection switching schemes and mapping strategies for fail-operational hard real-time NoCs. - Max Koenen; Nguyen Anh Vu Doan; Thomas Wild; Andreas Herkersdorf (Microprocess. Microsystems, 2021)

Exploring a Hybrid Voting-based Eviction Policy for Caches and Sparse Directories on Manycore Architectures. - Akshay Srivatsa; Nael Fasfous; Nguyen Anh Vu Doan; Sebastian Nagel 004; Thomas Wild; Andreas Herkersdorf (Microprocess. Microsystems, 2021)

GAE-LCT: A Run-Time GA-Based Classifier Evolution Method for Hardware LCT Controlled SoC Performance-Power Optimization. - Anmol Surhonne; Nguyen Anh Vu Doan; Florian Maurer 003; Thomas Wild; Andreas Herkersdorf (ARCS, 2022)

SmartNIC-based Load Management and Network Health Monitoring for Time Sensitive Applications. - Kilian Holzinger; Franz Biersack; Henning Stubbe; Angela Gonzalez Mariño; Abdoul Kane; Francesc Fons; Haigang Zhang; Thomas Wild; Andreas Herkersdorf; Georg Carle (NOMS, 2022)

GLS Tracing: Gem5-based Low-intrusive Software Tracing. - Lars Nolte; Tim Twardzik; Camille Jalier; Zhigang Huang; Jiyuan Shi; Thomas Wild; Andreas Herkersdorf (NorCAS, 2022)

Fine-Grained Power Modeling of Multicore Processors Using FFNNs. - Mark Sagi; Nguyen Anh Vu Doan; Nael Fasfous; Thomas Wild; Andreas Herkersdorf (Int. J. Parallel Program., 2022)

rmap: An R package to plot and compare tabular data on customizable maps across scenarios and time. - Zarrar Khan; Mengqi Zhao; Chris R. Vernon; Thomas Wild; Brinda Yarlagadda (J. Open Source Softw., 2022)

CoLeCTs: Cooperative Learning Classifier Tables for Resource Management in MPSoCs. - Klajd Zyla; Florian Maurer 003; Thomas Wild; Andreas Herkersdorf (ARCS, 2023)

HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification. - Lars Nolte; Tim Twardzik; Camille Jalier; Zhigang Huang; Jiyuan Shi; Clara Kowalsky; Thomas Wild; Andreas Herkersdorf (DAC, 2023)

LCT-DER: Learning Classifier Table with Dynamic-Sized Experience Replay for Run-time SoC Performance-Power Optimization. - Anmol Surhonne; Florian Maurer 003; Thomas Wild; Andreas Herkersdorf (GECCO Companion, 2023)

LCT-TL : Learning Classifier Table (LCT) with Transfer Learning for runtime SoC performance-power optimization. - Anmol Surhonne; Florian Maurer 003; Thomas Wild; Andreas Herkersdorf (MCSoC, 2023)

X-MAPE: Extending 6G-Connected Self-Adaptive Systems with Reflexive Actions. - Marco Liess; Julian Demicoli; Tobias Tiedje; Matthias Lohrmann; Matthias Nickel; M. Luniak; Dimitrios A. Prousalis; Thomas Wild; Ronald Tetzlaff; Diana Göhringer; Christian Mayr 001; Karlheinz Bock; et al. (NFV-SDN, 2023)

Priority-aware Inter-Server Receive Side Scaling. - Franz Biersack; Kilian Holzinger; Henning Stubbe; Thomas Wild; Georg Carle; Andreas Herkersdorf (PDP, 2023)

FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs. - Klajd Zyla; Marco Liess; Thomas Wild; Andreas Herkersdorf (VLSI-SoC, 2023)

Hardware Assist for Linux IPC on an FPGA Platform. - Lars Nolte; Tim Twardzik; Camille Jalier; Jiyuan Shi; Thomas Wild; Andreas Herkersdorf (CF, 2024)

HASIIL: Hardware-Assisted Scheduling to Improve IPC Latency in Linux. - Tim Twardzik; Lars Nolte; Camille Jalier; Jiyuan Shi; Thomas Wild; Andreas Herkersdorf (CF, 2024)

EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge. - Patrick Schmidt; Iuliia Topko; Matthias Stammler; Tanja Harbaum; Jürgen Becker 001; Rico Berner; Omar Ahmed; Jakub Jagielski; Thomas Seidler; Markus Abel; Marius Kreutzer; Maximilian Kirschner; et al. (DATE, 2024)

ecoNIC: Saving Energy Through SmartNIC-Based Load Balancing of Mixed-Critical Ethernet Traffic. - Franz Biersack; Marco Liess; Markus Absmann; Fabiana Lotter; Thomas Wild; Andreas Herkersdorf (DSD, 2024)

FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar. - Klajd Zyla; Marco Liess; Thomas Wild; Andreas Herkersdorf (DSD, 2024)

XCS with dynamic sized experience replay for memory constrained applications. - Anmol Surhonne; Manuel Wensauer; Florian Maurer 003; Thomas Wild; Andreas Herkersdorf (GECCO Companion, 2024)

QoS-Aware Dynamic Frequency Scaling for Mixed-Critical Systems based on Shielded Reinforcement Learning. - Florian Maurer 003; Michael Meidinger; Yiming Lu; Thomas Hallermeier; Anmol Surhonne; Thomas Wild; Andreas Herkersdorf (NorCAS, 2024)

FlexRoute: A Fast, Flexible and Priority-Aware Packet-Processing Design. - Klajd Zyla; Marco Liess; Thomas Wild; Andreas Herkersdorf (PDP, 2024)

HW-EPOLL: Hardware-Assisted User Space Event Notification for Epoll Syscall. - Lars Nolte; Tim Twardzik; Camille Jalier; Jiyuan Shi; Thomas Wild; Andreas Herkersdorf (SAMOS, 2024)

EPIC-Q: Equivalent-Policy Invariant Comparison Enhanced Transfer Q-learning for Run-Time SoC Performance-Power Optimization. - Anmol Surhonne; Haitham S. Fawzi; Florian Maurer 003; Oliver Lenke; Michael Meidinger; Thomas Wild; Andreas Herkersdorf (SAMOS, 2024)

HW-FUTEX: Hardware-Assisted Futex Syscall. - Lars Nolte; Tim Twardzik; Camille Jalier; Zhigang Huang; Jiyuan Shi; Thomas Wild; Andreas Herkersdorf (IEEE Trans. Very Large Scale Integr. Syst., 2024)

HiPerNoC: A High-Performance Network-an-Chip for Flexible and Scalable FPGA-Based SmartNICs. - Klajd Zyla; Marco Liess; Thomas Wild; Andreas Herkersdorf (DATE, 2025)