Prediction and Characterization of Frequency Dependent MOS Switch Linearity and the Design Implications. - Thomas William Brown; Terri S. Fiez; Mikko Hakkarainen (CICC, 2006)

Frequency-Dependent Sampling Linearity. - Thomas William Brown; Mikko Hakkarainen; Terri S. Fiez (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A 475 mV, 4.9 GHz enhanced swing differential Colpitts VCO in 130 nm CMOS with an FoM of 196.2 dBc/Hz. - Farhad Farhabakhshian; Thomas William Brown; Kartikeya Mayaram; Terri S. Fiez (CICC, 2010)

A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency. - Thomas William Brown; Farhad Farhabakhshian; Ankur Guha Roy; Terri S. Fiez; Kartikeya Mayaram (IEEE J. Solid State Circuits, 2011)

A 250 mV, 352 μ W GPS Receiver RF Front-End in 130 nm CMOS. - Adam C. Heiberg; Thomas William Brown; Terri S. Fiez; Kartikeya Mayaram (IEEE J. Solid State Circuits, 2011)

A 5G Sub-6GHz Zero-IF and mm-Wave IF Transceiver with MIMO and Carrier Aggregation. - Benjamin Jann; Greg Chance; Ankur Guha Roy; Aishwarya Balakrishnan; Niranjan Karandikar; Thomas William Brown; Xi Li; Brandon Davis; Jose Luis Ceballos; Nebil Tanzi; Kurt Hausmann; Hyun Yoon; et al. (ISSCC, 2019)

A 50 Gbps 134 GHz 16 QAM 3 m Dielectric Waveguide Transceiver System Implemented in 22nm CMOS. - Thomas William Brown; Georgios C. Dogiamis; Yi-Shin Yeh; Diego Correas-Serrano; Triveni S. Rane; Surej Ravikumar; Jessica C. Chou; Vijaya B. Neeli; Jose Mauricio Marulanda; Neelam Prabhu Gaunkar; Cho-Ying Lu; Iwen Huang; et al. (VLSI Circuits, 2021)

A 48dB-SFDR, 43dB-SNDR, 50GS/s 9-bit 2x-interleaved Nyquist DAC in Intel 16. - Hariprasad Chandrakumar; Thomas William Brown; Dimitri Frolov; Zinia Tuli; Iwen Huang; Said Rami (CICC, 2022)

A 128Gb/s 1.95pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET. - Abhishek Agrawal; Amy Whitcombe; Woorim Shin; Ritesh Bhat; Somnath Kundu; Peter Sagazio; Hariprasad Chandrakumar; Thomas William Brown; Brent R. Carlton; Christopher D. Hull; Steven Callender; Stefano Pellerano (ISSCC, 2023)

A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET. - Abhishek Agrawal; Amy Whitcombe; Woorim Shin; Ritesh Bhat; Somnath Kundu; Peter Sagazio; Hariprasad Chandrakumar; Thomas William Brown; Brent R. Carlton; Christopher Dennis Hull; Steven Callender; Stefano Pellerano (IEEE J. Solid State Circuits, 2023)

22.3 A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking. - Amy Whitcombe; Somnath Kundu; Hariprasad Chandrakumar; Abhishek Agrawal; Thomas William Brown; Steven Callender; Brent R. Carlton; Stefano Pellerano (ISSCC, 2024)