Migrating from planar to FinFET for further CMOS scaling: SOI or bulk? - Thomas Chiarella; Liesbeth Witters; Abdelkarim Mercha; Christoph Kerner; Rok Dittrich; Michal Rakowski; Claude Ortolland; Lars-Åke Ragnarsson; Bertrand Parvais; An De Keersgieter; Stefan Kubicek; Augusto Redolfi; et al. (ESSCIRC, 2009)

Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling. - Felice Crupi; Massimo Alioto; Jacopo Franco; Paolo Magnone; Ben Kaczer; Guido Groeseneken; Jérôme Mitard; Liesbeth Witters; Thomas Y. Hoffmann (ISCAS, 2011)

Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling. - Felice Crupi; Massimo Alioto; Jacopo Franco; Paolo Magnone; Ben Kaczer; Guido Groeseneken; Jérôme Mitard; Liesbeth Witters; Thomas Y. Hoffmann (IEEE Trans. Very Large Scale Integr. Syst., 2012)