Lattice Boltzmann Simulation and Visualisation of Adsorption Processes in Complex Geometries. - Jörg Bernsdorf; Uwe Jaekel; Thomas Zeiser; T. Takei; H. Matsumoto; K. Nishizawa (International Conference on Computational Science, 2003)

Performance Evaluation of Parallel Large-Scale Lattice Boltzmann Applications on Three Supercomputing Architectures. - Thomas Pohl; Frank Deserno; Nils Thürey; Ulrich Rüde; Peter Lammers; Gerhard Wellein; Thomas Zeiser (SC, 2004)

RZBENCH: Performance evaluation of current HPC architectures using low-level and application benchmarks - Georg Hager; Holger Stengel; Thomas Zeiser; Gerhard Wellein (CoRR, 2007)

Vector Computers in a World of Commodity Clusters, Massively Parallel Systems and Many-Core Many-Threaded CPUs: Recent Experience Based on an Advanced Lattice Boltzmann Flow Solver. - Thomas Zeiser; Georg Hager; Gerhard Wellein (High Performance Computing in Science and Engineering, 2008)

Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers. - Georg Hager; Thomas Zeiser; Gerhard Wellein (IPDPS, 2008)

Performance comparison of different parallel lattice Boltzmann implementations on multi-core multi-socket systems. - Stefan Donath; Klaus Iglberger; Gerhard Wellein; Thomas Zeiser; Aditya Nitsure; Ulrich Rüde (Int. J. Comput. Sci. Eng., 2008)

Performance evaluation of a parallel sparse lattice Boltzmann solver. - Lilit Axner; Jörg Bernsdorf; Thomas Zeiser; Peter Lammers; Jan Linxweiler; Alfons G. Hoekstra (J. Comput. Phys., 2008)

Data Access Characteristics and Optimizations for Sun UltraSPARC T2 and T2+ Systems. - Georg Hager; Thomas Zeiser; Gerhard Wellein (Parallel Process. Lett., 2008)

Efficient Temporal Blocking for Stencil Computations by Multicore-Aware Wavefront Parallelization. - Gerhard Wellein; Georg Hager; Thomas Zeiser; Markus Wittmann; Holger Fehske (COMPSAC (1), 2009)

The world's fastest CPU and SMP node: Some performance results from the NEC SX-9. - Thomas Zeiser; Georg Hager; Gerhard Wellein (IPDPS, 2009)

Benchmark Analysis and Application Results for Lattice Boltzmann Simulations on NEC SX Vector and Intel Nehalem Systems. - Thomas Zeiser; Georg Hager; Gerhard Wellein (Parallel Process. Lett., 2009)

Performance analysis and optimization strategies for a D3Q19 lattice Boltzmann kernel on nVIDIA GPUs using CUDA. - Johannes Habich; Thomas Zeiser; Georg Hager; Gerhard Wellein (Adv. Eng. Softw., 2011)

Comparison of different Propagation Steps for the Lattice Boltzmann Method - Markus Wittmann; Thomas Zeiser; Georg Hager; Gerhard Wellein (CoRR, 2011)

Domain decomposition and locality optimization for large-scale lattice Boltzmann simulations - Markus Wittmann; Thomas Zeiser; Georg Hager; Gerhard Wellein (CoRR, 2011)

Asynchronous Checkpointing by Dedicated Checkpoint Threads. - Faisal Shahzad 001; Markus Wittmann; Thomas Zeiser; Gerhard Wellein (EuroMPI, 2012)

An Evaluation of Different I/O Techniques for Checkpoint/Restart. - Faisal Shahzad 001; Markus Wittmann; Thomas Zeiser; Georg Hager; Gerhard Wellein (IPDPS Workshops, 2013)

Comparison of different propagation steps for lattice Boltzmann methods. - Markus Wittmann; Thomas Zeiser; Georg Hager; Gerhard Wellein (Comput. Math. Appl., 2013)

Asynchronous MPI for the Masses - Markus Wittmann; Georg Hager; Thomas Zeiser; Gerhard Wellein (CoRR, 2013)

An analysis of energy-optimized lattice-Boltzmann CFD simulations from the chip to the highly parallel level - Markus Wittmann; Georg Hager; Thomas Zeiser; Gerhard Wellein (CoRR, 2013)

A Survey of Checkpoint/Restart Techniques on Distributed Memory Systems. - Faisal Shahzad 001; Markus Wittmann; Moritz Kreutzer; Thomas Zeiser; Georg Hager; Gerhard Wellein (Parallel Process. Lett., 2013)

Modeling and analyzing performance for highly optimized propagation steps of the lattice Boltzmann method on sparse lattices. - Markus Wittmann; Thomas Zeiser; Georg Hager; Gerhard Wellein (CoRR, 2014)

Building a Fault Tolerant Application Using the GASPI Communication Layer. - Faisal Shahzad 001; Moritz Kreutzer; Thomas Zeiser; Rui Machado; Andreas Pieper; Georg Hager; Gerhard Wellein (CLUSTER, 2015)

Extreme Scale-out SuperMUC Phase 2 - lessons learned. - Nicolay Hammer; Ferdinand Jamitzky; Helmut Satzger; Momme Allalen; Alexander Block; Anupam Karmakar; Matthias Brehm; Reinhold Bader; Luigi Iapichino; Antonio Ragagnin; Vasilios Karakasis; Dieter Kranzlmüller; et al. (PARCO, 2015)

Short Note on Costs of Floating Point Operations on current x86-64 Architectures: Denormals, Overflow, Underflow, and Division by Zero. - Markus Wittmann; Thomas Zeiser; Georg Hager; Gerhard Wellein (CoRR, 2015)

Chip-level and multi-node analysis of energy-optimized lattice Boltzmann CFD simulations. - Markus Wittmann; Georg Hager; Thomas Zeiser; Jan Treibig; Gerhard Wellein (Concurr. Comput. Pract. Exp., 2016)

Lattice Boltzmann Benchmark Kernels as a Testbed for Performance Analysis. - Markus Wittmann; Viktor Haag; Thomas Zeiser; Harald Köstler; Gerhard Wellein (CoRR, 2017)

Building and utilizing fault tolerance support tools for the GASPI applications. - Faisal Shahzad 001; Moritz Kreutzer; Thomas Zeiser; Rui Machado; Andreas Pieper; Georg Hager; Gerhard Wellein (Int. J. High Perform. Comput. Appl., 2018)

ClusterCockpit - A web application for job-specific performance monitoring. - Jan Eitzinger; Thomas Gruber; Ayesha Afzal; Thomas Zeiser; Gerhard Wellein (CLUSTER, 2019)

CRAFT: A Library for Easier Application-Level Checkpoint/Restart and Automatic Fault Tolerance. - Faisal Shahzad 001; Jonas Thies; Moritz Kreutzer; Thomas Zeiser; Georg Hager; Gerhard Wellein (IEEE Trans. Parallel Distributed Syst., 2019)

What does Power Consumption Behavior of HPC Jobs Reveal? : Demystifying, Quantifying, and Predicting Power Consumption Characteristics. - Tirthak Patel; Adam Wagenhäuser; Christopher Eibel; Timo Hönig; Thomas Zeiser; Devesh Tiwari (IPDPS, 2020)