Static Power Side-Channel Analysis of a Threshold Implementation Prototype Chip. - Thorben Moos; Amir Moradi 001; Bastian Richter 001 (IACR Cryptol. ePrint Arch., 2016)

On the Easiness of Turning Higher-Order Leakages into First-Order. - Thorben Moos; Amir Moradi 001 (IACR Cryptol. ePrint Arch., 2017)

Static Power Side-Channel Analysis - A Survey on Measurement Factors. - Thorben Moos; Amir Moradi 001; Bastian Richter 001 (IACR Cryptol. ePrint Arch., 2018)

Exploring the Effect of Device Aging on Static Power Analysis Attacks. - Naghmeh Karimi; Thorben Moos; Amir Moradi 001 (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019)

Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments. - Thorben Moos (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019)

Glitch-Resistant Masking Revisited or Why Proofs in the Robust Probing Model are Needed. - Thorben Moos; Amir Moradi 001; Tobias Schneider 002; François-Xavier Standaert (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019)

PRINCEv2 - More Security for (Almost) No Overhead. - Dusan Bozilov; Maria Eichlseder; Miroslav Knezevic; Baptiste Lambin; Gregor Leander; Thorben Moos; Ventzislav Nikov; Shahram Rasoolzadeh; Yosuke Todo; Friedrich Wiemer (IACR Cryptol. ePrint Arch., 2020)

BSPL: Balanced Static Power Logic. - Bijan Fadaeinia; Thorben Moos; Amir Moradi 001 (IACR Cryptol. ePrint Arch., 2020)

The Risk of Outsourcing: Hidden SCA Trojans in Third-Party IP-Cores Threaten Cryptographic ICs. - David Knichel; Thorben Moos; Amir Moradi 001 (IACR Cryptol. ePrint Arch., 2020)

Unrolled Cryptography on Silicon A Physical Security Analysis. - Thorben Moos (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020)

Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations. - Samaneh Ghandali; Thorben Moos; Amir Moradi 001; Christof Paar (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Static Power Side-Channel Analysis - An Investigation of Measurement Factors. - Thorben Moos; Amir Moradi 001; Bastian Richter 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Low-Latency Hardware Masking of PRINCE. - Nicolai Müller; Thorben Moos; Amir Moradi 001 (IACR Cryptol. ePrint Arch., 2021)

The SPEEDY Family of Block Ciphers Engineering an Ultra Low-Latency Cipher from Gate Level for Secure Processor Architectures. - Gregor Leander; Thorben Moos; Amir Moradi 001; Shahram Rasoolzadeh (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021)

Let's Take it Offline: Boosting Brute-Force Attacks on iPhone's User Authentication through SCA. - Oleksiy Lisovets; David Knichel; Thorben Moos; Amir Moradi 001 (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021)

Countermeasures against Static Power Attacks - Comparing Exhaustive Logic Balancing and Other Protection Schemes in 28 nm CMOS -. - Thorben Moos; Amir Moradi 001 (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021)

DL-LA: Deep Learning Leakage Assessment A modern roadmap for SCA evaluations. - Thorben Moos; Felix Wegener; Amir Moradi 001 (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021)

Effective and Efficient Masking with Low Noise using Small-Mersenne-Prime Ciphers. - Loïc Masure; Pierrick Méaux; Thorben Moos; François-Xavier Standaert (IACR Cryptol. ePrint Arch., 2022)

Red Team vs. Blue Team: A Real-World Hardware Trojan Detection Case Study Across Four Modern CMOS Technology Generations. - Endres Puschner; Thorben Moos; Steffen Becker 003; Christian Kison; Amir Moradi 001; Christof Paar (IACR Cryptol. ePrint Arch., 2022)

Beware of Insufficient Redundancy An Experimental Evaluation of Code-based FI Countermeasures. - Timo Bartkewitz; Sven Bettendorf; Thorben Moos; Amir Moradi 001; Falk Schellenberg (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

Physical security for next generation CMOS ICs. - Thorben Moos (2022)

Energy Consumption of Protected Cryptographic Hardware Cores - An Experimental Study. - Aein Rezaei Shahmirzadi; Thorben Moos; Amir Moradi 001 (COSADE, 2023)

Combined Private Circuits - Combined Security Refurbished. - Jakob Feldtkeller; Tim Güneysu; Thorben Moos; Jan Richter-Brockmann; Sayandeep Saha; Pascal Sasdrich; François-Xavier Standaert (IACR Cryptol. ePrint Arch., 2023)

Prime-Field Masking in Hardware and its Soundness against Low-Noise SCA Attacks. - Gaëtan Cassiers; Loïc Masure; Charles Momin; Thorben Moos; François-Xavier Standaert (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023)

Generalized Feistel Ciphers for Efficient Prime Field Masking. - Lorenzo Grassi 001; Loïc Masure; Pierrick Méaux; Thorben Moos; François-Xavier Standaert (EUROCRYPT (3), 2024)

Randomness Generation for Secure Hardware Masking - Unrolled Trivium to the Rescue. - Gaëtan Cassiers; Loïc Masure; Charles Momin; Thorben Moos; Amir Moradi 001; François-Xavier Standaert (IACR Commun. Cryptol., 2024)

Generalized Feistel Ciphers for Efficient Prime Field Masking - Full Version. - Lorenzo Grassi 001; Loïc Masure; Pierrick Méaux; Thorben Moos; François-Xavier Standaert (IACR Cryptol. ePrint Arch., 2024)

Static Leakage in Dual-Rail Precharge Logics. - Bijan Fadaeinia; Thorben Moos; Amir Moradi 001 (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024)

Prime Masking vs. Faults - Exponential Security Amplification against Selected Classes of Attacks. - Thorben Moos; Sayandeep Saha; François-Xavier Standaert (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024)

On Borrowed Time - Preventing Static Side-Channel Analysis. - Robert Dumitru 002; Thorben Moos; Andrew Wabnitz; Yuval Yarom (NDSS, 2025)

mid-pSquare: Leveraging the Strong Side-Channel Security of Prime-Field Masking in Software. - Brieuc Balon; Lorenzo Grassi 001; Pierrick Méaux; Thorben Moos; François-Xavier Standaert; Matthias Johann Steiner (IACR Cryptol. ePrint Arch., 2025)

Fly Away: Lifting Fault Security through Canaries and the Uniform Random Fault Model. - Gaëtan Cassiers; Siemen Dhooghe; Thorben Moos; Sayandeep Saha; François-Xavier Standaert (IACR Cryptol. ePrint Arch., 2025)