Architecture and implementation of the reliable router. - William J. Dally; Larry R. Dennison; David Money Harris; Kinhong Kan; Thucydides Xanthopoulos (Hot Interconnects, 1994)

The Reliable Router: A Reliable and High-Performance Communication Substrate for Parallel Computers. - William J. Dally; Larry R. Dennison; David Money Harris; Kinhong Kan; Thucydides Xanthopoulos (PCRCW, 1994)

Low-latency plesiochronous data retiming. - Larry R. Dennison; William J. Dally; Thucydides Xanthopoulos (ARVLSI, 1995)

Data driven signal processing: an approach for energy efficient computing. - Anantha P. Chandrakasan; Vadim Gutnik; Thucydides Xanthopoulos (ISLPED, 1996)

Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT. - Thucydides Xanthopoulos; Yoshifumi Yaoi; Anantha P. Chandrakasan (DAC, 1997)

An ultra low power variable length decoder for MPEG-2 exploiting codeword distribution. - Seong-Hwan Cho; Thucydides Xanthopoulos; Anantha P. Chandrakasan (CICC, 1998)

Power scalable processing using distributed arithmetic. - Rajeevan Amirtharajah; Thucydides Xanthopoulos; Anantha P. Chandrakasan (ISLPED, 1999)

A low-power IDCT macrocell for MPEG-2 MP@ML exploiting data distribution properties for minimal activity. - Thucydides Xanthopoulos; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 1999)

A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning. - Seong-Hwan Cho; Thucydides Xanthopoulos; Anantha P. Chandrakasan (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Low power data-dependent transform video and still image coding. - Thucydides Xanthopoulos (1999)

A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization. - Thucydides Xanthopoulos; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2000)

Introduction to the Special Issue on the ISSCC2004. - Georgios K. Konstadinidis; Anantha P. Chandrakasan; Sreedhar Natarajan; Thucydides Xanthopoulos (IEEE J. Solid State Circuits, 2005)

A 16-Core RISC Microprocessor with Network Extensions. - Vishnu Yalala; Derek Brasili; David Carlson; Adam Hughes; Anil Jain; Tim Kiszely; Kolar Kodandapani; Anand Varadharajan; Thucydides Xanthopoulos (ISSCC, 2006)

Clocking. - Thucydides Xanthopoulos; Atila Alvandpour (ISSCC, 2007)

Can Multicore Integration Justify the Increased Cost of Process Scalling? - Thucydides Xanthopoulos; Don Draper (ISSCC, 2008)

Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring. - Kyoungho Woo; Scott E. Meninger; Thucydides Xanthopoulos; Ethan Crain; Dongwan Ha; Donhee Ham (ISSCC, 2009)

A 32-core RISC microprocessor with network accelerators, power management and testability features. - Brian Miller; Derek Brasili; Tim Kiszely; Rob Kuhn; Rahul Mehrotra; Manan Salvi; Mandar Kulkarni; Anand Varadharajan; Shi-Huang Yin; William Lin; Adam Hughes; Bill Stysiack; et al. (ISSCC, 2012)

Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring. - Dongwan Ha; Kyoungho Woo; Scott E. Meninger; Thucydides Xanthopoulos; Ethan Crain; Donhee Ham (IEEE Trans. Very Large Scale Integr. Syst., 2012)