Fast disjoint transistor networks from BDDs. - Leomar S. da Rosa Jr.; Felipe S. Marques 001; Tiago Muller Gil Cardoso; Renato P. Ribas; Sachin S. Sapatnekar; André Inácio Reis (SBCCI, 2006)

Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. - Tiago Muller Gil Cardoso; Leomar S. da Rosa Jr.; Felipe de Souza Marques; Renato P. Ribas; André Inácio Reis (ISQED, 2008)