On the accuracy of Elmore-based Delay Models. - Glauco B. V. dos Santos; Tiago Reimann; Marcelo de Oliveira Johann; Ricardo Augusto da Luz Reis (ICECS, 2009)

The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms. - Glauco Borges Valim dos Santos; Tiago Reimann; Marcelo O. Johann; Ricardo Reis 001 (ICCD, 2010)

Routing algorithms performance in different routing scopes. - Tiago Reimann; Glauco B. V. dos Santos; Ricardo A. L. Reis (ICECS, 2010)

Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing. - Tiago Reimann; Gracieli Posser; Guilherme Flach; Marcelo O. Johann; Ricardo Reis 001 (ISCAS, 2013)

Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities. - Guilherme Flach; Tiago Reimann; Gracieli Posser; Marcelo O. Johann; Ricardo Reis 001 (ISVLSI, 2013)

GR-PA: A cost pre-allocation model for global routing. - Leandro Nunes; Tiago Reimann; Ricardo Reis 001 (VLSI-SoC, 2013)

Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation. - Guilherme Flach; Tiago Reimann; Gracieli Posser; Marcelo O. Johann; Ricardo Reis 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Gate sizing and threshold voltage assignment for high performance microprocessor designs. - Tiago Reimann; Cliff C. N. Sze; Ricardo Reis 001 (ASP-DAC, 2015)

Cell Selection for High-Performance Designs in an Industrial Design Flow. - Tiago J. Reimann; Cliff C. N. Sze; Ricardo Reis 001 (ISPD, 2016)

Challenges of cell selection algorithms in industrial high performance microprocessor designs. - Tiago Reimann; Cliff C. N. Sze; Ricardo Reis 001 (Integr., 2016)

Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations. - Ankur Sharma 001; David G. Chinnery; Tiago Reimann; Sarvesh Bhardwaj; Chris Chu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)