Scalable memory architecture for soft-core processors. - Tiago T. Jost; Gabriel L. Nazar; Luigi Carro (ICCD, 2016)

Improving performance in VLIW soft-core processors through software-controlled scratchpads. - Tiago T. Jost; Gabriel L. Nazar; Luigi Carro (SAMOS, 2016)

An energy-efficient memory hierarchy for multi-issue processors. - Tiago T. Jost; Gabriel L. Nazar; Luigi Carro (DATE, 2017)

A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs. - Pedro Henrique Exenberger Becker; Anderson Luiz Sartor; Marcelo Brandalero; Tiago Trevisan Jost; Stephan Wong; Luigi Carro; Antonio C. S. Beck (ARC, 2018)

Evaluation of approximate operators case study: sobel filter application executed on an approximate RISC-V platform. - Geneviève Ndour; Tiago Trevisan Jost; Anca Molnos; Yves Durand; Arnaud Tisserand (SAMOS, 2018)

Evaluation of variable bit-width units in a RISC-V processor for approximate computing. - Geneviève Ndour; Tiago Trevisan Jost; Anca Molnos; Yves Durand; Arnaud Tisserand (CF, 2019)

Byte-Aware Floating-point Operations through a UNUM Computing Unit. - Andrea Bocco; Tiago T. Jost; Albert Cohen 001; Florent de Dinechin; Yves Durand; Christian Fabre (VLSI-SoC, 2019)

VP Float: First Class Treatment for Variable Precision Floating Point Arithmetic. - Tiago T. Jost; Yves Durand; Christian Fabre; Albert Cohen 001; Frédéric Pétrot (PACT, 2020)

SoMMA: A software-managed memory architecture for multi-issue processors. - Tiago Trevisan Jost; Gabriel Luca Nazar; Luigi Carro (Microprocess. Microsystems, 2020)

Seamless Compiler Integration of Variable Precision Floating-Point Arithmetic. - Tiago Trevisan Jost; Yves Durand; Christian Fabre; Albert Cohen 001; Frédéric Pétrot (CGO, 2021)

Compilation and optimizations for variable precision floating-Point arithmetic : from language and libraries to code generation. (Compilation et optimisations pour l'arithmétique à virgule flottante en précision variable : du langage et des bibliothèques à la génération de code). - Tiago Trevisan Jost (2021)

Lifting Code Generation of Cardiac Physiology Simulation to Novel Compiler Technology. - Arun Thangamani; Tiago Trevisan Jost; Vincent Loechner; Stéphane Genaud; Bérenger Bramas (CGO, 2023)

GPU Code Generation of Cardiac Electrophysiology Simulation with MLIR. - Tiago Trevisan Jost; Arun Thangamani; Raphaël Colin; Vincent Loechner; Stéphane Genaud; Bérenger Bramas (Euro-Par, 2023)