A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling. - Biao He; Shuhan Zhang; Yifan Wang; Tianning Gao; Fan Yang 001; Changhao Yan; Dian Zhou; Zhaori Bi; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

ROI-HIT: Region of Interest-Driven High-Dimensional Microarchitecture Design Space Exploration. - Xuyang Zhao; Tianning Gao; Aidong Zhao; Zhaori Bi; Changhao Yan; Fan Yang 001; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An RISC-V PPA-Fusion Cooperative Optimization Framework Based on Hybrid Strategies. - Tianning Gao; Yifan Wang; Ming Zhu 016; Xiulong Wu; Dian Zhou; Zhaori Bi (IEEE Trans. Very Large Scale Integr. Syst., 2025)

APPLE-DSE: Asynchronous Parallel Pareto Set Learning for Microarchitecture Design Space Exploration. - Xuyang Zhao; Tianning Gao; Zheng Wu; Zhaori Bi; Changhao Yan; Fan Yang 001; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)