Detailed electrical and reliability study of tapered TSVs. - Tiantao Lu; Ankur Srivastava 001 (3DIC, 2013)

Gated low-power clock tree synthesis for 3D-ICs. - Tiantao Lu; Ankur Srivastava 001 (ISLPED, 2014)

Electromigration-aware Clock Tree Synthesis for TSV-based 3D-ICs. - Tiantao Lu; Ankur Srivastava 001 (ACM Great Lakes Symposium on VLSI, 2015)

Modeling and Layout Optimization for Tapered TSVs. - Tiantao Lu; Ankur Srivastava 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs. - Tiantao Lu; Caleb Serafy; Zhiyuan Yang 001; Ankur Srivastava 001 (ISLPED, 2016)

Electromigration-aware placement for 3D-ICs. - Tiantao Lu; Zhiyuan Yang 001; Ankur Srivastava 001 (ISQED, 2016)

Post-Placement Optimization for Thermal-Induced Mechanical Stress Reduction. - Tiantao Lu; Zhiyuan Yang 001; Ankur Srivastava 001 (ISVLSI, 2016)

Security and Vulnerability Implications of 3D ICs. - Yang Xie 001; Chongxi Bao; Caleb Serafy; Tiantao Lu; Ankur Srivastava 001; Mark Tehranipoor (IEEE Trans. Multi Scale Comput. Syst., 2016)

Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors. - Zhiyuan Yang 001; Caleb Serafy; Tiantao Lu; Ankur Srivastava 001 (DAC, 2017)

TSV-Based 3-D ICs: Design Methods and Tools. - Tiantao Lu; Caleb Serafy; Zhiyuan Yang 001; Sandeep Kumar Samal; Sung Kyu Lim; Ankur Srivastava 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Low-Power Clock Tree Synthesis for 3D-ICs. - Tiantao Lu; Ankur Srivastava 001 (ACM Trans. Design Autom. Electr. Syst., 2017)

Enhanced Phase-Driven Q-Learning-Based DRM for Multicore Processors. - Zhiyuan Yang 001; Caleb Serafy; Tiantao Lu; Ankur Srivastava 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)