Suppression of VCO pulling effects using even-harmonic quiet transmitting circuits. - Yue Wu; Tianyu Jia; Bo Xia; Xinlong Ma; Li Kang; Xiaodong Yang (ESSCIRC, 2015)

Model Transformation and Data Migration from Relational Database to MongoDB. - Tianyu Jia; Xiaomeng Zhao; Zheng Wang 001; Dahan Gong; Guiguang Ding (BigData Congress, 2016)

Exploration of associative power management with instruction governed operation for ultra-low power design. - Tianyu Jia; Yuanbo Fan; Russ Joseph; Jie Gu 001 (DAC, 2016)

Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management. - Tianyu Jia; Russ Joseph; Jie Gu 001 (DAC, 2017)

(Invited) Software-guided greybox design methodology with integrated power and clock management. - Tianyu Jia; Yuanbo Fan; Russ Joseph; Jie Gu 001 (MWSCAS, 2017)

A Fully-integrated LC-Oscillator Based Buck Regulator with Autonomous Resonant Switching for Low-Power Applications. - Tianyu Jia; Jie Gu 001 (A-SSCC, 2018)

Compiler-guided instruction-level clock scheduling for timing speculative processors. - Yuanbo Fan; Tianyu Jia; Jie Gu 001; Simone Campanoni; Russ Joseph (DAC, 2018)

An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. - Tianyu Jia; Russ Joseph; Jie Gu 001 (ESSCIRC, 2018)

Design and optimization of edge computing distributed neural processor for biomedical rehabilitation with sensor fusion. - Kofi Otseidu; Tianyu Jia; Joshua Bryne; Levi J. Hargrove; Jie Gu 001 (ICCAD, 2018)

Holistic Energy Management with μProcessor Co-Optimization in Fully Integrated Battery-Less IoTs. - Josiah D. Hester; Tianyu Jia; Jie Gu 001 (SoCC, 2018)

A Fully Integrated Buck Regulator With 2-GHz Resonant Switching for Low-Power Applications. - Tianyu Jia; Jie Gu 001 (IEEE J. Solid State Circuits, 2018)

Words in Kitchen: An Instance of Leveraging Virtual Reality Technology to Learn Vocabulary. - Tianyu Jia; Yue Liu (ISMAR Adjunct, 2019)

An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution. - Tianyu Jia; Russ Joseph; Jie Gu 001 (ISSCC, 2019)

A 48 V Input 0.75 V Output DC-DC Converter Power Block for HPC Systems and Datacenters (invited paper). - Todd Takken; Andrew Ferencz; Chung-Shiang Wu; Liam McAuliffe; Tianyu Jia; Xin Zhang (VLSI Circuits, 2019)

An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor. - Tianyu Jia; Russ Joseph; Jie Gu 001 (IEEE J. Solid State Circuits, 2019)

31.3 A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators. - Tianyu Jia; Yuhao Ju; Jie Gu 001 (ISSCC, 2020)

NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance. - Tianyu Jia; Yuhao Ju; Russ Joseph; Jie Gu 001 (MICRO, 2020)

Small-Dimension Feature Matrix Construction Method for Decoding Repetitive Finger Movements From Electroencephalogram Signals. - Tianyu Jia; Ke Liu; Yijia Lu; Yali Liu; Chong Li 004; Linhong Ji; Chao Qian 008 (IEEE Access, 2020)

An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture. - Tianyu Jia; Yijie Wei; Russ Joseph; Jie Gu 001 (IEEE J. Solid State Circuits, 2020)

FlexACC: A Programmable Accelerator with Application-Specific ISA for Flexible Deep Neural Network Inference. - En-Yu Yang; Tianyu Jia; David Brooks 001; Gu-Yeon Wei (ASAP, 2021)

Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems. - Zishen Wan; Aqeel Anwar; Yu-Shun Hsiao; Tianyu Jia; Vijay Janapa Reddi; Arijit Raychowdhury (DAC, 2021)

5 Hz rTMS improves motor-imagery based BCI classification performance. - Tianyu Jia; Linhong Mo; Chong Li 004; Aixian Liu; Zhibin Li 004; Linhong Ji (EMBC, 2021)

EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference. - Thierry Tambe; Coleman Hooper; Lillian Pentecost; Tianyu Jia; En-Yu Yang; Marco Donato; Victor Sanh; Paul N. Whatmough; Alexander M. Rush; David Brooks 001; Gu-Yeon Wei (MICRO, 2021)

MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles. - Yu-Shun Hsiao; Zishen Wan; Tianyu Jia; Radhika Ghosal; Arijit Raychowdhury; David Brooks 001; Gu-Yeon Wei; Vijay Janapa Reddi (CoRR, 2021)

A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique. - Tianyu Jia; Yuhao Ju; Jie Gu 001 (IEEE J. Solid State Circuits, 2021)

OMU: A Probabilistic 3D Occupancy Mapping Accelerator for Real-time OctoMap at the Edge. - Tianyu Jia; En-Yu Yang; Yu-Shun Hsiao; Jonathan J. Cruz; David Brooks 001; Gu-Yeon Wei; Vijay Janapa Reddi (DATE, 2022)

FRL-FI: Transient Fault Analysis for Federated Reinforcement Learning-Based Navigation Systems. - Zishen Wan; Aqeel Anwar; Abdulrahman Mahmoud; Tianyu Jia; Yu-Shun Hsiao; Vijay Janapa Reddi; Arijit Raychowdhury (DATE, 2022)

A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC. - Tianyu Jia; Paolo Mantovani; Maico Cassel dos Santos; Davide Giri; Joseph Zuckerman; Erik Jens Loscalzo; Martin Cochet; Karthik Swaminathan; Gabriele Tombesi; Jeff Jun Zhang; Nandhini Chandramoorthy; John-David Wellman; et al. (ESSCIRC, 2022)

A Differentiable Neural Computer for Logic Reasoning with Scalable Near-Memory Computing and Sparsity Based Enhancement. - Yuhao Ju; Shiyu Guo; Zixuan Liu; Tianyu Jia; Jie Gu 001 (ESSCIRC, 2022)

A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components. - Maico Cassel dos Santos; Tianyu Jia; Martin Cochet; Karthik Swaminathan; Joseph Zuckerman; Paolo Mantovani; Davide Giri; Jeff Jun Zhang; Erik Jens Loscalzo; Gabriele Tombesi; Kevin Tien; Nandhini Chandramoorthy; et al. (ICCAD, 2022)

Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration. - Georgios Zacharopoulos; Adel Ejjeh; Ying Jing; En-Yu Yang; Tianyu Jia; Iulian Brumar; Jeremy Intan; Muhammad Huzaifa; Sarita V. Adve; Vikram S. Adve; Gu-Yeon Wei; David Brooks 001 (CoRR, 2022)

A 65nm Fully-integrated Fast-switching Buck Converter with Resonant Gate Drive and Automatic Tracking. - Xi Chen 099; Aly Shoukry; Tianyu Jia; Xin Zhang 025; Raveesh Magod; Nachiket V. Desai; Jie Gu 001 (CICC, 2023)

A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology. - Ying Liu 069; Zhiyuan Chen 009; Zhixuan Wang; Wentao Zhao; Wei He; Jianfeng Zhu; Oijun Wang; Ning Zhang; Tianyu Jia; Yufei Ma 002; Le Ye; Ru Huang 001 (CICC, 2023)

A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware. - Yanchi Dong; Tianyu Jia; Kaixuan Du; Yiqi Jing; Qijun Wang; Pixian Zhan; Yadong Zhang; Fengyun Yan; Yufei Ma 002; Yun Liang 001; Le Ye; Ru Huang 001 (DAC, 2023)

MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles. - Yu-Shun Hsiao; Zishen Wan; Tianyu Jia; Radhika Ghosal; Abdulrahman Mahmoud; Arijit Raychowdhury; David Brooks 001; Gu-Yeon Wei; Vijay Janapa Reddi (DATE, 2023)

ARES: A Mapping Framework of DNNs Towards Diverse PIMs with General Abstractions. - Xiuping Cui; Size Zheng 001; Tianyu Jia; Le Ye; Yun Liang 001 (ICCAD, 2023)

DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler. - Yiqi Jing; Yiyang Sun; Xiao Wang; Wentao Zhao; Meng Wu 005; Fengyun Yan; Yufei Ma 002; Le Ye; Tianyu Jia (ISLPED, 2023)

A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing. - Peiyu Chen; Meng Wu 005; Wentao Zhao; Jiajia Cui; Zhixuan Wang; Yadong Zhang; Qijun Wang; Jiayoon Ru; Linxiao Shen; Tianyu Jia; Yufei Ma 002; Le Ye; et al. (ISSCC, 2023)

A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management. - Thierry Tambe; Jeff Zhang 001; Coleman Hooper; Tianyu Jia; Paul N. Whatmough; Joseph Zuckerman; Maico Cassel dos Santos; Erik Jens Loscalzo; Davide Giri; Kenneth L. Shepard; Luca P. Carloni; Alexander M. Rush; et al. (ISSCC, 2023)

Multi-Agent Robust Control Synthesis from Global Temporal Logic Tasks. - Tiange Yang; Yuanyuan Zou 001; Jinfeng Liu 001; Tianyu Jia; Shaoyuan Li (CoRR, 2023)

Spatio-Temporal Evolution of Inland Lakes and Their Relationship with Hydro-Meteorological Factors in Horqin Sandy Land, China. - Yiran Zhang; Xin Tong; Tingxi Liu; Limin Duan; Lina Hao; Vijay P. Singh; Tianyu Jia; Shuo Lun (Remote. Sens., 2023)

Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration. - Georgios Zacharopoulos; Adel Ejjeh; Ying Jing; En-Yu Yang; Tianyu Jia; Iulian Brumar; Jeremy Intan; Muhammad Huzaifa; Sarita V. Adve; Vikram S. Adve; Gu-Yeon Wei; David Brooks 001 (ACM Trans. Embed. Comput. Syst., 2023)

Research progress on low-power artificial intelligence of things (AIoT) chip design. - Le Ye; Zhixuan Wang; Tianyu Jia; Yufei Ma 002; Linxiao Shen; Yihan Zhang 002; Heyi Li; Peiyu Chen; Meng Wu 005; Ying Liu 069; Yiqi Jing; Hao Zhang 119; et al. (Sci. China Inf. Sci., 2023)

SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs. - Gabriele Tombesi; Joseph Zuckerman; Paolo Mantovani; Davide Giri; Maico Cassel dos Santos; Tianyu Jia; David Brooks 001; Gu-Yeon Wei; Luca P. Carloni (IEEE Des. Test, 2023)

Time Robust Model Predictive Control for Heterogeneous Multi-Agent Systems Under Global Temporal Logic Tasks. - Tiange Yang; Yuanyuan Zou 001; Jinfeng Liu 001; Tianyu Jia; Shaoyuan Li (ACC, 2024)

Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow. - Yikan Qiu; Yufei Ma 002; Meng Wu 005; Yifan Jia 009; Xinyu Qu; Zecheng Zhou; Jincheng Lou; Tianyu Jia; Le Ye; Ru Huang 001 (CICC, 2024)

S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications. - Meng Wu 005; Wenjie Ren; Peiyu Chen; Wentao Zhao; Yiqi Jing; Jiayoon Ru; Zhixuan Wang; Yufei Ma 002; Ru Huang 001; Tianyu Jia; Le Ye (CICC, 2024)

An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology. - Zhiyuan Chen 009; Yufei Ma 002; Keyi Li; Yifan Jia 009; Guoxiang Li; Meng Wu 005; Tianyu Jia; Le Ye; Ru Huang 001 (DAC, 2024)

AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration. - Yiqi Jing; Meng Wu 005; Jiaqi Zhou; Yiyang Sun; Yufei Ma 002; Ru Huang 001; Tianyu Jia; Le Ye (DAC, 2024)

SPARK: An Efficient Hybrid Acceleration Architecture with Run-Time Sparsity-Aware Scheduling for TinyML Learning. - Mingxuan Li; Qinzhe Zhi; Yanchi Dong; Le Ye; Tianyu Jia (DAC, 2024)

Enhancing Motor Learning Performance by Incorporating Brain-to-brain Coupling with Affective Interaction. - Feiyu Pan; Tianyu Jia; Jingyao Sun; Annie Yan Wang; Linhong Ji; Chong Li 004 (EMBC, 2024)

Unsupervised Gait Assessments of Stroke Patients Using a Smartphone and Machine Learning. - Jingyao Sun; Tianyu Jia; Kiensiau Lim; Linhong Mo; Linhong Ji; Chong Li 004 (EMBC, 2024)

Hierarchical Power Co-Optimization and Management for LLM Chiplet Designs. - Yanchi Dong; Xueping Liu; Xiaochen Hao; Yun Liang 001; Ru Huang 001; Le Ye; Tianyu Jia (ICCAD, 2024)

ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC. - Qipan Wang; Xueqing Li; Tianyu Jia; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2024)

BlitzCoin: Fully Decentralized Hardware Power Management for Accelerator-Rich SoCs. - Martin Cochet; Karthik Swaminathan; Erik Jens Loscalzo; Joseph Zuckerman; Maico Cassel dos Santos; Davide Giri; Alper Buyuktosunoglu; Tianyu Jia; David Brooks 001; Gu-Yeon Wei; Kenneth L. Shepard; Luca P. Carloni; et al. (ISCA, 2024)

30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing. - Ying Liu 069; Yufei Ma 002; Ninghui Shang; Tianhao Zhao; Peiyu Chen; Meng Wu 005; Jiayoon Ru; Tianyu Jia; Le Ye; Zhixuan Wang; Ru Huang 001 (ISSCC, 2024)

14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration. - Maico Cassel dos Santos; Tianyu Jia; Joseph Zuckerman; Martin Cochet; Davide Giri; Erik Jens Loscalzo; Karthik Swaminathan; Thierry Tambe; Jeff Jun Zhang; Alper Buyuktosunoglu; Kuan-Lin Chiu; Giuseppe Di Guglielmo; et al. (ISSCC, 2024)

Learning Cortico-Muscular Dependence through Orthonormal Decomposition of Density Ratios. - Shihan Ma; Bo Hu; Tianyu Jia; Alexander Kenneth Clarke; Blanka Zicher; Arnault H. Caillet; Dario Farina; José C. Príncipe (NeurIPS, 2024)

A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup. - Yanchi Dong; Xueping Liu; Kangbo Bai; Guoxiang Li; Meng Wu 005; Yiqi Jing; Yihan Zhang 002; Pixian Zhan; Yadong Zhang; Yufei Ma 002; Ru Huang 001; Le Ye; et al. (VLSI Technology and Circuits, 2024)

A 400-ns-Settling- Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology. - Erik Jens Loscalzo; Martin Cochet; Joseph Zuckerman; Samira Zalias; Michael Lekas; Stephen Cahill; Tianyu Jia; Karthik Swaminathan; Maico Cassel dos Santos; Davide Giri; Hesam Sadeghi; Joseph Meyer; et al. (VLSI Technology and Circuits, 2024)

Multiscale Canonical Coherence for Functional Corticomuscular Coupling Analysis. - Jingyao Sun; Tianyu Jia; Ping-Ju Lin; Zhibin Li 004; Linhong Ji; Chong Li 004 (IEEE J. Biomed. Health Informatics, 2024)

Silent Data Corruption in Robot Operating System: A Case for End-to-End System-Level Fault Analysis Using Autonomous UAVs. - Yu-Shun Hsiao; Zishen Wan; Tianyu Jia; Radhika Ghosal; Abdulrahman Mahmoud; Arijit Raychowdhury; David Brooks 001; Gu-Yeon Wei; Vijay Janapa Reddi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network. - Ying Liu 069; Zhiyuan Chen 009; Wentao Zhao; Tianhao Zhao; Tianyu Jia; Zhixuan Wang; Ru Huang 001; Le Ye; Yufei Ma 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network. - Yufei Ma 002; Yikan Qiu; Wentao Zhao; Guoxiang Li; Meng Wu 005; Tianyu Jia; Le Ye; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

GSNorm: An Efficient 3D Gaussian Rendering Accelerator with Splat Normalization and LUT-assist Rasterization. - Yiyang Sun; Peiran Yan; Yiqi Jing; Le Ye; Tianyu Jia (ASP-DAC, 2025)

Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUs. - Zhantong Zhu; Hongou Li; Wenjie Ren; Meng Wu 005; Le Ye; Ru Huang 001; Tianyu Jia (DATE, 2025)

Improving Driving Performance in Difficult Driving Scenarios Using Personalized Real-Time Neurofeedback. - Jian Shi; Zhen Zhang; Lishengsha Yue; Tianyu Jia; Yang Yufeng (HCI (52), 2025)

A 22nm All-digital Fully Synthesizable Adaptive Clock Generator for Fast Frequency Adjustment in AI Processor. - Xueping Liu; Le Ye; Tianyu Jia (ISCAS, 2025)

37.6 A 22nm 60.81TFLOPS/W Diffusion Accelerator with Bandwidth-Aware Memory Partition and BL-Segmented Compute-in-Memory for Efficient Multi-Task Content Generation. - Yiqi Jing; Jiaqi Zhou; Yiyang Sun; Siyuan He; Peiyu Chen; Ru Huang 001; Le Ye; Tianyu Jia (ISSCC, 2025)

A synergistic UAV-Landsat novel strategy for enhanced estimation of above-ground biomass and shrub dominance in Sandy land. - Yiran Zhang; Tingxi Liu; Asaad Y. Shamseldin; Xin Tong; Limin Duan; Tianyu Jia; Shuo Lun; Simin Zhang (Ecol. Informatics, 2025)

Stackelberg Game Preference Optimization for Data-Efficient Alignment of Language Models. - Xu Chu; Zhixin Zhang; Tianyu Jia; Yujie Jin (CoRR, 2025)

Patch-wise Structural Loss for Time Series Forecasting. - Dilfira Kudrat; Zongxia Xie; Yanru Sun; Tianyu Jia; Qinghua Hu (CoRR, 2025)

Lightweight Channel-wise Dynamic Fusion Model: Non-stationary Time Series Forecasting via Entropy Analysis. - Tianyu Jia; Zongxia Xie; Yanru Sun; Dilfira Kudrat; Qinghua Hu (CoRR, 2025)

Structured and sparse partial least squares coherence for multivariate cortico-muscular analysis. - Jingyao Sun; Qilu Zhang; Di Ma; Tianyu Jia; Shijie Jia; Xiaoxue Zhai; Ruimou Xie; Ping-Ju Lin; Zhibin Li 004; Yu Pan; Linhong Ji; Chong Li 004 (CoRR, 2025)

Cortical Activation Patterns Determine Effectiveness of rTMS-Induced Motor Imagery Decoding Enhancement in Stroke Patients. - Tianyu Jia; Linhong Mo; Ciarán McGeady; Jingyao Sun; Aixian Liu; Linhong Ji; Jianing Xi; Chong Li 004 (IEEE Trans. Biomed. Eng., 2025)

LearNAT: Learning NL2SQL with AST-guided Task Decomposition for Large Language Models. - Weibin Liao; Xin Gao; Tianyu Jia; Rihong Qiu; Yifan Zhu; Yang Lin; Xu Chu; Junfeng Zhao 001; Yasha Wang (CoRR, 2025)

Global Temporal Logic Control Synthesis for Multiagent Systems With Time and Space Margin. - Tiange Yang; Jinfeng Liu 001; Yuanyuan Zou 001; Tianyu Jia; Shaoyuan Li (IEEE Trans. Ind. Electron., 2025)

EdgeMM: Multi-Core CPU with Heterogeneous AI-Extension and Activation-aware Weight Pruning for Multimodal LLMs at Edge. - Kangbo Bai; Le Ye; Ru Huang 001; Tianyu Jia (CoRR, 2025)

LP-Spec: Leveraging LPDDR PIM for Efficient LLM Mobile Speculative Inference with Architecture-Dataflow Co-Optimization. - Siyuan He; Zhantong Zhu; Yandong He; Tianyu Jia (CoRR, 2025)

Tasa: Thermal-aware 3D-Stacked Architecture Design with Bandwidth Sharing for LLM Inference. - Siyuan He; Peiran Yan; Yandong He; Youwei Zhuo; Tianyu Jia (CoRR, 2025)

A 22-nm Delta-Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing. - Peiyu Chen; Wentao Zhao; Meng Wu 005; Linxiao Shen; Tianyu Jia; Ru Huang 001; Le Ye; Yufei Ma 002 (IEEE J. Solid State Circuits, 2025)