Low-Latency Asynchronous FIFO's Using Token Rings. - Tiberiu Chelcea; Steven M. Nowick (ASYNC, 2000)

Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols. - Tiberiu Chelcea; Steven M. Nowick (DAC, 2001)

A Burst-Mode Oriented Back-End for the Balsa Synthesis System. - Tiberiu Chelcea; Steven M. Nowick; Andrew Bardsley; Doug A. Edwards (DATE, 2002)

Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems. - Tiberiu Chelcea; Steven M. Nowick (IWLS, 2002)

Spatial computation. - Mihai Budiu; Girish Venkataramani; Tiberiu Chelcea; Seth Copen Goldstein (ASPLOS, 2004)

Robust interfaces for mixed-timing systems. - Tiberiu Chelcea; Steven M. Nowick (IEEE Trans. Very Large Scale Integr. Syst., 2004)

SOMA: a tool for synthesizing and optimizing memory accesses in ASICs. - Girish Venkataramani; Tiberiu Chelcea; Seth Copen Goldstein; Tobias Bjerregaard (CODES+ISSS, 2005)

Tartan: evaluating spatial computation for whole program execution. - Mahim Mishra; Timothy J. Callahan; Tiberiu Chelcea; Girish Venkataramani; Seth Copen Goldstein; Mihai Budiu (ASPLOS, 2006)

Hardware compilation of application-specific memory-access interconnect. - Girish Venkataramani; Tobias Bjerregaard; Tiberiu Chelcea; Seth Copen Goldstein (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis. - Tiberiu Chelcea; Girish Venkataramani; Seth Copen Goldstein (ASYNC, 2007)

Self-Resetting Latches for Asynchronous Micro-Pipelines. - Tiberiu Chelcea; Girish Venkataramani; Seth Copen Goldstein (DAC, 2007)

Global Critical Path: A Tool for System-Level Timing Analysis. - Girish Venkataramani; Mihai Budiu; Tiberiu Chelcea; Seth Copen Goldstein (DAC, 2007)

Heterogeneous Latch-Based Asynchronous Pipelines. - Girish Venkataramani; Tiberiu Chelcea; Seth Copen Goldstein (ASYNC, 2008)