A low power high area-efficiency NMOS LDO with fast adaptive bias. - Tiedong Cheng; Ziyu Xiao; Jianping Guo; Lijun Xu (Integr., 2023)

Modeling threshold voltage and drain-induced barrier lowering effect of opposite doping core-shell channel surrounding-gate junctionless MOSFET. - Lijun Xu; Guitai Wu; Pei Li; Tiedong Cheng (Microelectron. J., 2023)

A 8.83 ppm/°C temperature coefficient, 75 dB PSRR subthreshold CMOS voltage reference with piecewise curvature compensation. - Tiedong Cheng; Hao Rao; Jinxiang Wei (Integr., 2024)

A 1 V supply 10.3 ppm/°C 59 nW subthreshold CMOS voltage reference. - Tiedong Cheng; Xinlv Gong (Microelectron. J., 2024)