A methodology for power characterization of associative memories. - Dawei Li; Siddhartha Joshi; Seda Ogrenci Memik; James Hoff; Sergo Jindariani; Tiehui Liu 001; Jamieson Olsen; Nhan Tran (ICCD, 2015)

A content addressable memory with multi-Vdd scheme for low power tunable operation. - Siddhartha Joshi; Dawei Li; Seda Ogrenci Memik; Grzegorz Deptuch; James Hoff; Sergo Jindariani; Tiehui Liu 001; Jamieson Olsen; Nhan Tran (MWSCAS, 2017)

A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade. - Wei Zhang; Hanhan Sun; Christopher Edwards; Datao Gong; Xing Huang; Chonghan Liu; Tiankuan Liu; Tiehui Liu 001; Jamieson Olsen; Quan Sun; Xiangming Sun; Jinyuan Wu; et al. (CoRR, 2020)

A 2.56-GS/s 12-bit 8x-Interleaved ADC With 156.6-dB FoMS in 65-nm CMOS. - Liang Fang; Xianshan Wen; Tao Fu; Guanhua Wang; Sandeep Miryala; Tiehui Ted Liu; Ping Gui (IEEE Trans. Very Large Scale Integr. Syst., 2022)