A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application. - Mu-Shan Lin; Chien-Chun Tsai; Chih-Hsien Chang; Wen-Hung Huang; Ying-Yu Hsu; Shu-Chun Yang; Chin-Ming Fu; Mao-Hsuan Chou; Tien-Chien Huang; Ching-Fang Chen; Tze-Chiang Huang; Saman Adham; et al. (IEEE J. Solid State Circuits, 2014)

A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. - Chao-Chieh Li; Tsung-Hsien Tsai; Min-Shueh Yuan; Chia-Chun Liao; Chih-Hsien Chang; Tien-Chien Huang; Hsien-Yuan Liao; Chung-Ting Lu; Hung-Yi Kuo; Kenny Hsieh; Mark Chen 001; Augusto Ronchini Ximenes; et al. (VLSI Circuits, 2016)

A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS. - Chao-Chieh Li; Min-Shueh Yuan; Chia-Chun Liao; Chih-Hsien Chang; Yu-Tso Lin; Tsung-Hsien Tsai; Tien-Chien Huang; Hsien-Yuan Liao; Chung-Ting Lu; Hung-Yi Kuo; Augusto Ronchini Ximenes; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)