An effective on-chip preloading scheme to reduce data access penalty. - Jean-Loup Baer; Tien-Fu Chen (SC, 1991)

Reducing Memory Latency via Non-blocking and Prefetching Caches. - Tien-Fu Chen; Jean-Loup Baer (ASPLOS, 1992)

An Evaluation of Hardware and Software Data Prefetching. - Jean-Loup Baer; Tien-Fu Chen (Applications in Parallel and Distributed Computing, 1994)

A Performance Study of Software and Hardware Data Prefetching Schemes. - Tien-Fu Chen; Jean-Loup Baer (ISCA, 1994)

An effective programmable prefetch engine for on-chip caches. - Tien-Fu Chen (MICRO, 1995)

Effective Hardware Based Data Prefetching for High-Performance Processors. - Tien-Fu Chen; Jean-Loup Baer (IEEE Trans. Computers, 1995)

Efficient trace-sampling simulation techniques for cache performance analysis. - Tien-Fu Chen (Annual Simulation Symposium, 1996)

Techniques for The Efficient Analysis of Cache Performance. - Tien-Fu Chen (J. Inf. Sci. Eng., 1996)

Reducing memory penalty by a programmable prefetch engine for on-chip caches. - Tien-Fu Chen (Microprocess. Microsystems, 1997)

Supporting Highly-Speculative Execution via Adaptive Branch Trees. - Tien-Fu Chen (HPCA, 1998)

SBA: a server-initiated playback scheme supporting variable bit rate control. - Jung-Long Jiang; Tien-Fu Chen (IEEE Trans. Consumer Electron., 1999)

Segmented bus design for low-power systems. - J.-Y. Chen; Wen-Ben Jone; Jinn-Shyan Wang; Hsueh-I Lu; Tien-Fu Chen (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Dynamic memory management for real-time embedded Java chips. - Chi-Min Lin; Tien-Fu Chen (RTCSA, 2000)

Compressing inverted files in scalable information systems by binary decision diagram encoding . - Chung-Hung Lai; Tien-Fu Chen (SC, 2001)

Dynamic voltage leveling scheduling for real-time embedded systems on low-power variable speed processors. - Jian-Liang Kuo; Tien-Fu Chen (CASES, 2002)

Posting file partitioning and parallel information retrieval. - Yung-Cheng Ma; Tien-Fu Chen; Chung-Ping Chung (J. Syst. Softw., 2002)

Decoupling of data and tag arrays for on-chip caches. - Tien-Fu Chen; Yi-Min Hwang (Microprocess. Microsystems, 2002)

A Tree-Based inverted File for Fast Ranked-Document Retrieval. - Wann-Yun Shieh; Tien-Fu Chen; Chung-Ping Chung (IKE, 2003)

Flexible Heterogeneous Multicore Architectures for Media Processing via Customized Long Instruction Words. - Chia-Ming Hsu; Tien-Fu Chen (VLSI-SOC, 2003)

Inverted file compression through document identifier reassignment. - Wann-Yun Shieh; Tien-Fu Chen; Jean Jyh-Jiun Shann; Chung-Ping Chung (Inf. Process. Manag., 2003)

Energy Efficient Caching-on-Cache Architectures for Embedded Systems. - Hung-Cheng Wu; Tien-Fu Chen; Hung-Yu Li; Jinn-Shyan Wang (J. Inf. Sci. Eng., 2003)

Variable-size data item placement for load and storage balancing. - Yung-Cheng Ma; Jih-Ching Chiu; Tien-Fu Chen; Chung-Ping Chung (J. Syst. Softw., 2003)

A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. - Kuan-Hung Chen; Jiun-In Guo; Jinn-Shyan Wang; Ching-Wei Yeh; Tien-Fu Chen (ISCAS (2), 2004)

Unified bus encoding by stream reconstruction with variable strides. - Tien-Fu Chen; Tsung-Ming Hsieh; Chun-Li Wei (ISCAS (2), 2004)

A power-aware IP core generator for the one-dimensional discrete Fourier transform. - Chih-Da Chien; Chien-Chang Lin; Jiun-In Guo; Tien-Fu Chen (ISCAS (3), 2004)

A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT. - Rei-Chin Ju; Jia-Wei Chen; Jiun-In Guo; Tien-Fu Chen (ISCAS (2), 2004)

Scalable locality-aware event dispatching mechanism for network servers. - Hao-Ran Liu; Tien-Fu Chen (IEE Proc. Softw., 2004)

Branch-and-bound task allocation with task clustering-based pruning. - Yung-Cheng Ma; Tien-Fu Chen; Chung-Ping Chung (J. Parallel Distributed Comput., 2004)

Crossroad System-on-Chip Communication Architecture for Low Power Embedded Systems. - Kuei-Chung Chang; Jih-Sheng Shen; Tien-Fu Chen (ESA, 2005)

System-Level Power-Aware Scheduling by Operation-based Prediction. - Kuei-Chung Chang; Tien-Fu Chen; Wei-Yen Chuang (PSC, 2005)

Efficient Segment-Based Video Transcoding Proxy for Mobile Multimedia Services. - Kuei-Chung Chang; Ren-Yo Wu; Tien-Fu Chen (ICME, 2005)

A low-power crossroad switch architecture and its core placement for network-on-chip. - Kuei-Chung Chang; Jih-Sheng Shen; Tien-Fu Chen (ISLPED, 2005)

Development of Architecture and Software Technologies in High-Performance Low-Power SoC Design. - Chih-wen Hsueh; Tien-Fu Chen; Rong-Guey Chang; Shi-Wu Lo (RTCSA, 2005)

Design techniques for single-low-VDD CMOS systems. - Jinn-Shyan Wang; Hung-Yu Li; Chingwei Yeh; Tien-Fu Chen (IEEE J. Solid State Circuits, 2005)

Flexible Heterogeneous Multicore Architectures for Versatile Media Processing Via Customized Long Instruction Words. - Tien-Fu Chen; Chia-Ming Hsu; S.-R. Wu (IEEE Trans. Circuits Syst. Video Technol., 2005)

Fast Run-Time Power Monitoring Methodology for Embedded Systems. - Kuei-Chung Chang; Jih-Sheng Shen; Tien-Fu Chen (ESA, 2006)

Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs. - Kuei-Chung Chang; Jih-Sheng Shen; Tien-Fu Chen (DAC, 2006)

Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications. - Wei-Chun Ku; Shu-Hsuan Chou; Jui-Chin Chu; Chih-Heng Kang; Tien-Fu Chen; Jiun-In Guo (ICME, 2006)

Design of customized functional units for the VLIW-based multi-threading processor core targeted at multimedia applications. - Jui-Chin Chu; Chih-Wen Huang; He-Chun Chen; Keng-Po Lu; Ming-Shuan Lee; Jiun-In Guo; Tien-Fu Chen (ISCAS, 2006)

On a design of crossroad switches for low-power on-chip communication architectures. - Jih-Sheng Shen; Kuei-Chung Chang; Tien-Fu Chen (ISCAS, 2006)

An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model. - Jui-Chin Chu; Wei-Chun Ku; Shu-Hsuan Chou; Tien-Fu Chen; Jiun-In Guo (DAC, 2007)

Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling. - Chang-Ching Yeh; Kuei-Chung Chang; Tien-Fu Chen; Chingwei Yeh (HiPEAC, 2007)

Efficient segment-based video transcoding proxy for mobile multimedia services. - Kuei-Chung Chang; Tien-Fu Chen (J. Syst. Archit., 2007)

Low-power algorithm for automatic topology generation for application-specific networks on chips. - Kuei-Chung Chang; Tien-Fu Chen (IET Comput. Digit. Tech., 2008)

Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes. - Kuei-Chung Chang; Jih-Sheng Shen; Tien-Fu Chen (ACM Trans. Design Autom. Electr. Syst., 2008)

No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips. - Shu-Hsuan Chou; Chien-Chih Chen; Chi-Neng Wen; Yi-Chao Chan; Tien-Fu Chen; Chao-Ching Wang; Jinn-Shyan Wang (DAC, 2009)

NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core. - Chi-Neng Wen; Shu-Hsuan Chou; Tien-Fu Chen; Alan Peisheng Su (DAC, 2009)

dIP: A Non-intrusive Debugging IP for Dynamic Data Race Detection in Many-Core. - Chi-Neng Wen; Shu-Hsuan Chou; Tien-Fu Chen (ISPAN, 2009)

VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models. - Shu-Hsuan Chou; Chi-Neng Wen; Yan-Ling Liu; Tien-Fu Chen (ISQED, 2009)

An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices. - Chao-Ching Wang; Chieh-Jen Cheng; Tien-Fu Chen; Jinn-Shyan Wang (IEEE J. Solid State Circuits, 2009)

VisoMT: A Collaborative Multithreading Multicore Processor for Multimedia Applications With a Fast Data Switching Mechanism. - Wei-Chun Ku; Shu-Hsuan Chou; Jui-Chin Chu; Chi-Lin Liu; Tien-Fu Chen; Jiun-In Guo; Jinn-Shyan Wang (IEEE Trans. Circuits Syst. Video Technol., 2009)

RunAssert: A non-intrusive run-time assertion for parallel programs debugging. - Chi-Neng Wen; Shu-Hsuan Chou; Tien-Fu Chen; Tay-Jyi Lin (DATE, 2010)

Adaptive Pipeline voltage Scaling in High Performance Microprocessor. - Chang-Ching Yeh; Kuei-Chung Chang; Tien-Fu Chen; Chingwei Yeh (J. Circuits Syst. Comput., 2010)

Load and storage balanced posting file partitioning for parallel information retrieval. - Yung-Cheng Ma; Chung-Ping Chung; Tien-Fu Chen (J. Syst. Softw., 2011)

Hierarchical circuit-switched NoC for multicore video processing. - Shu-Hsuan Chou; Chien-Chih Chen; Chi-Neng Wen; Tien-Fu Chen; Tay-Jyi Lin (Microprocess. Microsystems, 2011)

Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategy. - Chang-Ching Yeh; Kuei-Chung Chang; Tien-Fu Chen; Chingwei Yeh (ACM Trans. Archit. Code Optim., 2011)

IMITATOR: A deterministic multicore replay system with refining techniques. - Shing-Yu Chen; Chi-Neng Wen; Geng-Hau Yang; Wen-Ben Jone; Tien-Fu Chen (VLSI-DAT, 2012)

NUDA: A Non-Uniform Debugging Architecture and Nonintrusive Race Detection for Many-Core Systems. - Chi-Neng Wen; Shu-Hsuan Chou; Chien-Chih Chen; Tien-Fu Chen (IEEE Trans. Computers, 2012)

A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security. - Chieh-Jen Cheng; Chao-Ching Wang; Wei-Chun Ku; Tien-Fu Chen; Jinn-Shyan Wang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. - Tay-Jyi Lin; Cheng-An Chien; Pei-Yao Chang; Ching-Wen Chen; Po-Hao Wang; Ting-Yu Shyu; Chien-Yung Chou; Shien-Chun Luo; Jiun-In Guo; Tien-Fu Chen; Gene C. H. Chuang; Yuan-Hua Chu; et al. (ISSCC, 2013)

A configurable bus-tracer for error reproduction in post-silicon validation. - Shing-Yu Chen; Ming-Yi Hsiao; Wen-Ben Jone; Tien-Fu Chen (VLSI-DAT, 2013)

Cross-layer dynamic prefetching allocation strategies for high-performance multicores. - Yin-Chi Peng; Chien-Chih Chen; Chia-Jung Chang; Tien-Fu Chen; Pen-Chung Yew (VLSI-DAT, 2013)

Variation-aware and adaptive-latency accesses for reliable low voltage caches. - Po-Hao Wang; Wei-Chung Cheng; Yung-Hui Yu; Tang-Chieh Kao; Chi-Lun Tsai; Pei-Yao Chang; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (VLSI-SoC, 2013)

DAPs: Dynamic Adjustment and Partial Sampling for Multithreaded/Multicore Simulation. - Chien-Chih Chen; Yin-Chi Peng; Cheng-Fen Chen; Wei-Shan Wu; Qinghao Min; Pen-Chung Yew; Weihua Zhang; Tien-Fu Chen (DAC, 2014)

Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination. - Hsiang-Jen Tsai; Chien-Chih Chen; Keng-Hao Yang; Ting-Chin Yang; Li-Yue Huang; Ching-Hao Chuang; Meng-Fan Chang; Tien-Fu Chen (DAC, 2014)

ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing. - Li-Yue Huang; Meng-Fan Chang; Ching-Hao Chuang; Chia-Chen Kuo; Chien-Fu Chen; Geng-Hau Yang; Hsiang-Jen Tsai; Tien-Fu Chen; Shyh-Shyuan Sheu; Keng-Li Su; Frederick T. Chen; Tzu-Kun Ku; et al. (VLSIC, 2014)

Reconfigurable vertical profiling framework for the android runtime system. - Tzu-Hsiang Su; Hsiang-Jen Tsai; Keng-Hao Yang; Po-Chun Chang; Tien-Fu Chen; Yi-Ting Zhao (ACM Trans. Embed. Comput. Syst., 2014)

Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. - Pei-Yuan Chou; I-Chen Wu; Jai-Wei Lin; Xuan-Yu Lin; Tien-Fu Chen; Tay-Jyi Lin; Jinn-Shyan Wang (ASICON, 2015)

Energy-efficient non-volatile TCAM search engine design using priority-decision in memory technology for DPI. - Hsiang-Jen Tsai; Keng-Hao Yang; Yin-Chi Peng; Chien-Chen Lin; Ya-Han Tsao; Meng-Fan Chang; Tien-Fu Chen (DAC, 2015)

17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time. - Meng-Fan Chang; Chien-Chen Lin; Albert Lee; Chia-Chen Kuo; Geng-Hau Yang; Hsiang-Jen Tsai; Tien-Fu Chen; Shyh-Shyuan Sheu; Pei-Ling Tseng; Heng-Yuan Lee; Tzu-Kun Ku (ISSCC, 2015)

Adaptive granularity and coordinated management for timely prefetching in multi-core systems. - Chia-Jung Chang; Yin-Chi Peng; Chien-Chih Chen; Tien-Fu Chen; Pen-Chung Yew (VLSI-DAT, 2015)

Lifetime-aware LRU promotion policy for last-level cache. - Hong-Yi Wu; Chien-Chih Chen; Hsiang-Jen Tsai; Yin-Chi Peng; Tien-Fu Chen (VLSI-DAT, 2015)

A latency-elastic and fault-tolerant cache for improving performance and reliability on low voltage operation. - Yung-Hui Yu; Po-Hao Wang; Shang-Jen Tsai; Tien-Fu Chen (VLSI-DAT, 2015)

Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability. - Hsuan-Ming Chou; Ming-Yi Hsiao; Yi-Chiao Chen; Keng-Hao Yang; Jean Tsao; Chiao-Ling Lung; Shih-Chieh Chang; Wen-Ben Jone; Tien-Fu Chen (IEEE Trans. Very Large Scale Integr. Syst., 2015)

7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications. - Win-San Khwa; Meng-Fan Chang; Jau-Yi Wu; Ming-Hsiu Lee; Tzu-Hsiang Su; Keng-Hao Yang; Tien-Fu Chen; Tien-Yen Wang; Hsiang-Pang Li; Matthew BrightSky; SangBum Kim; Hsiang-Lam Lung; et al. (ISSCC, 2016)

7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell. - Chien-Chen Lin; Jui-Yu Hung; Wen-Zhang Lin; Chieh-Pu Lo; Yen-Ning Chiang; Hsiang-Jen Tsai; Geng-Hau Yang; Ya-Chin King; Chrong Jung Lin; Tien-Fu Chen; Meng-Fan Chang (ISSCC, 2016)

Variable-length VLIW encoding for code size reduction in embedded processors. - Ting-Yu Shyu; Bo-Yu Su; Tay-Jyi Lin; Chingwei Yeh; Jinn-Shyan Wang; Tien-Fu Chen (SoCC, 2016)

Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. - Po-Hao Wang; Shang-Jen Tsai; Rizal Tanjung; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (Integr., 2016)

A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing. - Meng-Fan Chang; Li-Yue Huang; Wen-Zhang Lin; Yen-Ning Chiang; Chia-Chen Kuo; Ching-Hao Chuang; Keng-Hao Yang; Hsiang-Jen Tsai; Tien-Fu Chen; Shyh-Shyuan Sheu (IEEE J. Solid State Circuits, 2016)

Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations. - Po-Hao Wang; Wei-Chung Cheng; Yung-Hui Yu; Tang-Chieh Kao; Chi-Lun Tsai; Pei-Yao Chang; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols. - Hsuan-Ming Chou; Yi-Chiao Chen; Keng-Hao Yang; Jean Tsao; Shih-Chieh Chang; Wen-Ben Jone; Tien-Fu Chen (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing. - Meng-Fan Chang; Chien-Chen Lin; Albert Lee; Yen-Ning Chiang; Chia-Chen Kuo; Geng-Hau Yang; Hsiang-Jen Tsai; Tien-Fu Chen; Shyh-Shyuan Sheu (IEEE J. Solid State Circuits, 2017)

A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications. - Win-San Khwa; Meng-Fan Chang; Jau-Yi Wu; Ming-Hsiu Lee; Tzu-Hsiang Su; Keng-Hao Yang; Tien-Fu Chen; Tien-Yen Wang; Hsiang-Pang Li; Matthew J. BrightSky; SangBum Kim; Hsiang-Lam Lung; et al. (IEEE J. Solid State Circuits, 2017)

eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache. - Keng-Hao Yang; Hsiang-Jen Tsai; Chia-Yin Li; Paul Jendra; Meng-Fan Chang; Tien-Fu Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control. - Yin-Chi Peng; Chien-Chih Chen; Hsiang-Jen Tsai; Keng-Hao Yang; Pei-Zhe Huang; Shih-Chieh Chang; Wen-Ben Jone; Tien-Fu Chen (ACM Trans. Design Autom. Electr. Syst., 2017)

A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata. - Hsiang-Jen Tsai; Chien-Chih Chen; Yin-Chi Peng; Ya-Han Tsao; Yen-Ning Chiang; Wei-Cheng Zhao; Meng-Fan Chang; Tien-Fu Chen (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology. - Hsiang-Jen Tsai; Keng-Hao Yang; Yin-Chi Peng; Chien-Chen Lin; Ya-Han Tsao; Meng-Fan Chang; Tien-Fu Chen (IEEE Trans. Very Large Scale Integr. Syst., 2017)

ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. - Po-Hao Wang; Yung-Chen Chien; Shang-Jen Tsai; Xuan-Yu Lin; Rizal Tanjung; Yi-Sian Lin; Shu-Wei Syu; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Adaptive Similarity-Aware Hyperparameter Tuners for Classification Tasks. - Chi-Lin Hsieh; Kuei-Chung Chang; Tien-Fu Chen (IEEE Access, 2023)

LLM4TS: Two-Stage Fine-Tuning for Time-Series Forecasting with Pre-Trained LLMs. - Ching Chang 001; Wen-Chih Peng; Tien-Fu Chen (CoRR, 2023)

A 40-nm 13.88-TOPS/W FC-DNN Engine for 16-bit Intelligent Audio Processing Featuring Weight-Sharing and Approximate Computing. - Tay-Jyi Lin; Ze Li; Yun-Cheng Chen; Chien-Tung Liu; Tien-Fu Chen; Jinn-Shyan Wang (HCS, 2024)

TimeDRL: Disentangled Representation Learning for Multivariate Time-Series. - Ching Chang 001; Chiao-Tung Chan; Wei-Yao Wang; Wen-Chih Peng; Tien-Fu Chen (ICDE, 2024)

Efficient Inference of Transformers on Bare-Metal Devices with RISC-V Vector Processors. - Yi-Xuan Huang; Po-Han Huang; Juin-Ming Lu; Tay-Jyi Lin; Tien-Fu Chen (NewCAS, 2024)

Hybrid Bayesian Optimization with Early Termination Strategies for Auto Tuning. - Hsiang-Cheng Hsieh; ShengPo Lin; Arbind Kumar Mahto; Kuei-Chung Chang; Juin-Ming Lu; Tay-Jyi Lin; Tien-Fu Chen (ISVLSI, 2025)

Enhancing Semi-Supervised Learners via Similarity-Based Self-Supervised Models. - ShengPo Lin; Hsiang-Cheng Hsieh; Lianzheng Lin; Kuei-Chung Chang; Juin-Ming Lu; Tay-Jyi Lin; Tien-Fu Chen (NewCAS, 2025)

Design Space Exploration for Scalable DNN Accelerators Using a Memory-Centric Analytical Model for HW/SW Co-Design. - Wei-Chun Huang; Chih-Wei Tang; Kuei-Chung Chang; Tien-Fu Chen; Hsiang-Cheng Hsieh; Ming-Hsuan Tsai (ACM Trans. Design Autom. Electr. Syst., 2025)

Time-IMM: A Dataset and Benchmark for Irregular Multimodal Multivariate Time Series. - Ching Chang; Jeehyun Hwang; Yidan Shi; Haixin Wang 003; Wen-Chih Peng; Tien-Fu Chen; Wei Wang 010 (CoRR, 2025)

PromptTSS: A Prompting-Based Approach for Interactive Multi-Granularity Time Series Segmentation. - Ching Chang; Ming-Chih Lo; Wen-Chih Peng; Tien-Fu Chen (CoRR, 2025)

LLM4TS: Aligning Pre-Trained LLMs as Data-Efficient Time-Series Forecasters. - Ching Chang 001; Wei-Yao Wang; Wen-Chih Peng; Tien-Fu Chen (ACM Trans. Intell. Syst. Technol., 2025)