The NVAX CPU Chip: Design Challenges, Methods, and CAD Tools. - Dale R. Donchin; Timothy C. Fischer; Thomas F. Fox; Victor Peng; Ronald P. Preston; William R. Wheeler (Digit. Tech. J., 1992)

A 100-MHz macropipelined VAX microprocessor. - Roy W. Badeau; R. Iris Bahar; Debra Bemstein; Larry L. Biro; William J. Bowhill; John F. Brown III; Michael A. Case; Ruben W. Castelino; Elizabeth M. Cooper; Maureen A. Delaney; David R. Deverell; John H. Edmondson; et al. (IEEE J. Solid State Circuits, 1992)

Internal Organization of the Alpha 21164, a 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor - John H. Edmondson; Paul I. Rubinfeld; Peter J. Bannon; Bradley J. Benschneider; Debra Bernstein; Ruben W. Castelino; Elizabeth M. Cooper; Daniel E. Dever; Dale R. Donchin; Timothy C. Fischer; Anil K. Jain 003; Shekhar Mehta; et al. (Digit. Tech. J., 1995)

Issue logic for a 600-MHz out-of-order execution microprocessor. - James A. Farrell; Timothy C. Fischer (IEEE J. Solid State Circuits, 1998)

The implementation of the Itanium 2 microprocessor. - Samuel D. Naffziger; Glenn Colón-Bonet; Timothy C. Fischer; Reid J. Riedlinger; Thomas J. Sullivan; Tom Grutkowski (IEEE J. Solid State Circuits, 2002)

A 90-nm variable frequency clock system for a power-managed itanium architecture processor. - Tim C. Fischer; Jayen Desai; Bruce Andrew Doyle; Samuel Naffziger; Ben Patella (IEEE J. Solid State Circuits, 2006)

Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU. - Tim C. Fischer; Srikanth Arekapudi; Eric Busta; Carl Dietz; Michael Golden; Scott Hilker; Aaron Horiuchi; Kevin A. Hurd; Dave Johnson 002; Hugh McIntyre; Samuel Naffziger; James Vinh; et al. (ISSCC, 2011)

Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS. - Hugh McIntyre; Srikanth Arekapudi; Eric Busta; Timothy C. Fischer; Michael Golden; Aaron Horiuchi; Tom Meneghini; Samuel Naffziger; James Vinh (IEEE J. Solid State Circuits, 2012)

Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference. - Maurits Ortmanns; Timothy C. Fischer; Uming Ko; Wim Dehaene; Yasuhiro Takai (IEEE J. Solid State Circuits, 2013)

Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions. - Timothy C. Fischer; Byeong-Gyu Nam; Leland Chang; Tadahiro Kuroda; Michiel A. P. Pertijs (IEEE J. Solid State Circuits, 2014)

D1: A 7nm ML Training Processor with Wave Clock Distribution. - Tim C. Fischer; Anantha Kumar Nivarti; Raghuvir Ramachandran; Ram Bharti; Derek Carson; Anton Lawrendra; Vineet Mudgal; Vivek Santhosh; Sunil Shukla; Te-Chen Tsai (ISSCC, 2023)

The Microarchitecture of DOJO, Tesla's Exa-Scale Computer. - Emil Talpes; Debjit Das Sarma; Douglas Williams; Sahil Arora; Thomas Kunjan; Benjamin Floering; Ankit Jalote; Christopher Hsiong; Chandrasekhar Poorna; Vaidehi Samant; John Sicilia; Anantha Kumar Nivarti; et al. (IEEE Micro, 2023)