Piepser: A Smart Wrist-Worn Variometer To Maximize The Paragliders Flytime. - Tim Fischer 001; Michael Ganz; Nicolas Baumann; Michele Magno (SAS, 2019)

MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores. - Luca Bertaccini; Gianna Paulin; Tim Fischer 001; Stefan Mach; Luca Benini (ARITH, 2022)

A 1036 TOp/s/W, 12.2 mW, 2.72 μJ/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML Applications. - Moritz Scherer 001; Alfio Di Mauro; Georg Rutishauser; Tim Fischer 001; Luca Benini (COOL CHIPS, 2022)

Ternarized TCN for $ mu mathrm{J}/ text{Inference}$ Gesture Recognition from DVS Event Frames. - Georg Rutishauser; Moritz Scherer 001; Tim Fischer 001; Luca Benini (DATE, 2022)

TCN-CUTIE: A 1036 TOp/s/W, 2.72 uJ/Inference, 12.2 mW All-Digital Ternary Accelerator in 22 nm FDX Technology. - Moritz Scherer 001; Alfio Di Mauro; Tim Fischer 001; Georg Rutishauser; Luca Benini (CoRR, 2022)

Sparse Hamming Graph: A Customizable Network-on-Chip Topology. - Patrick Iff; Maciej Besta; Matheus A. Cavalcante; Tim Fischer 001; Luca Benini; Torsten Hoefler (DAC, 2023)

HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement. - Patrick Iff; Maciej Besta; Matheus A. Cavalcante; Tim Fischer 001; Luca Benini; Torsten Hoefler (DAC, 2023)

ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers. - Gamze Islamoglu; Moritz Scherer 001; Gianna Paulin; Tim Fischer 001; Victor J. B. Jung; Angelo Garofalo; Luca Benini (ISLPED, 2023)

FlooNoC: A Multi-Tbps Wide NoC for Heterogeneous AXI4 Traffic. - Tim Fischer 001; Michael Rogenmoser; Matheus A. Cavalcante; Frank K. Gürkaynak; Luca Benini (CoRR, 2023)

TCN-CUTIE: A 1, 036-TOp/s/W, 2.72-µJ/Inference, 12.2-mW All-Digital Ternary Accelerator in 22-nm FDX Technology. - Moritz Scherer 001; Alfio Di Mauro; Tim Fischer 001; Georg Rutishauser; Luca Benini (IEEE Micro, 2023)

FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic. - Tim Fischer 001; Michael Rogenmoser; Matheus A. Cavalcante; Frank K. Gürkaynak; Luca Benini (IEEE Des. Test, 2023)

7 μJ/inference end-to-end gesture recognition from dynamic vision sensor data using ternarized hybrid convolutional neural networks. - Georg Rutishauser; Moritz Scherer 001; Tim Fischer 001; Luca Benini (Future Gener. Comput. Syst., 2023)

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. - Gianna Paulin; Paul Scheffler; Thomas Benz; Matheus A. Cavalcante; Tim Fischer 001; Manuel Eggimann; Yichao Zhang 003; Nils Wistoff; Luca Bertaccini; Luca Colagrande; Gianmarco Ottavi; Frank K. Gürkaynak; et al. (VLSI Technology and Circuits, 2024)

Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform. - Viviane Potocnik; Luca Colagrande; Tim Fischer 001; Luca Bertaccini; Daniele Jahier Pagliari; Alessio Burrello; Luca Benini (CoRR, 2024)

FlooNoC: A 645 Gbps/link 0.15 pJ/B/hop Open-Source NoC with Wide Physical Links and End-to-End AXI4 Parallel Multi-Stream Support. - Tim Fischer 001; Michael Rogenmoser; Thomas Benz; Frank K. Gürkaynak; Luca Benini (CoRR, 2024)

ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package. - Alessandro Ottaviano; Robert Balas; Tim Fischer 001; Thomas Benz; Andrea Bartolini; Luca Benini (CoRR, 2024)

MiniFloats on RISC-V Cores: ISA Extensions With Mixed-Precision Short Dot Products. - Luca Bertaccini; Gianna Paulin; Matheus A. Cavalcante; Tim Fischer 001; Stefan Mach; Luca Benini (IEEE Trans. Emerg. Top. Comput., 2024)

AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors. - Navaneeth Kunhi Purayil; Matteo Perotti; Tim Fischer 001; Luca Benini (DATE, 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (CoRR, 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (IEEE J. Solid State Circuits, 2025)

FlooNoC: A 645-Gb/s/link 0.15-pJ/B/hop Open-Source NoC With Wide Physical Links and End-to-End AXI4 Parallel Multistream Support. - Tim Fischer 001; Michael Rogenmoser; Thomas Benz; Frank K. Gürkaynak; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2025)