Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment. - Ranianand Venkata; Wilson Wong; Tina Tran; Vinson Chan; Tim Hoang; Henry Lui; Uinh Ton; Sergey Shomurryev; Chong Lee; Shoujun Waiig; Huy Ngo; Malik Kdhani; et al. (CICC, 2003)

Receiver Offset Cancellation in 90-nm PLD Integrated SERDES. - Simar Maangat; Toan Nguyen; Wilson Wong; Sergey Y. Shumarayev; Tina Tran; Tim Hoang; Richard Cliff (CICC, 2007)

Arria™ 10 device architecture. - Jeffrey Tyhach; Mike Hutton; Sean Atsatt; Arifur Rahman; Brad Vest; David M. Lewis; Martin Langhammer; Sergey Y. Shumarayev; Tim Hoang; Allen Chan; Dong-Myung Choi; Dan Oh; et al. (CICC, 2015)

Heterogenous Integration Enables FPGA Based Hardware Acceleration for RF Applications. - Sergey Y. Shumarayev; Allen Chan; Tim Hoang; Robert Keller (HCS, 2022)