Formal Verification of the Alpha 21364 Network Protocol. - Abdel Mokkedem; Tim Leonard (TPHOLs, 2000)

Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers. - Per Bjesse; Tim Leonard; Abdel Mokkedem (CAV, 2001)

Accelerated verification of RTL assertions based on satisfiability solvers. - Ranan Fraer; Shahid Ikram; Gila Kamhi; Tim Leonard; Abdel Mokkedem (HLDVT, 2002)

An FPGA Implementation of Explicit-State Model Checking. - Mary Ellen Fuess; Miriam Leeser; Tim Leonard (FCCM, 2008)

Extracting models from design documents with mapster. - David James; Tim Leonard; John W. O'Leary; Murali Talupur; Mark R. Tuttle (PODC, 2008)

Book review: Barbara Allan, Emerging Strategies for Supporting Student Learning. - Tim Leonard (J. Libr. Inf. Sci., 2021)