A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration. - Sumeet Singh Nagi; Uneeb Rathore; Krutikesh Sahoo; Tim Ling; Subramanian S. Iyer; Dejan Markovic (IEEE J. Solid State Circuits, 2023)