Architecture of a VLSI Instruction Cache for a RISC - David A. Patterson 001; Phil Garrison; Mark D. Hill; Dimitris Lioupis; Chris Nyberg; Tim Sippel; Korbin S. Van Dyke (ISCA, 1983)

A 533-MHz BiCMOS superscalar RISC microprocessor. - Cliff A. Maier; James A. Markevitch; Cheryl Senter Brashears; Tim Sippel; Earl T. Cohen; Jim Blomgren; James G. Ballard; Jay Pattin; Viki Moldenhauer; Jeffrey A. Thomas; George Taylor (IEEE J. Solid State Circuits, 1997)