Formal performance analysis and simulation of UML/SysML models for ESL design. - Alexander Viehl; Timo Schönwald; Oliver Bringmann 001; Wolfgang Rosenstiel (DATE, 2006)

Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures. - Timo Schönwald; Jochen Zimmermann; Oliver Bringmann 001; Wolfgang Rosenstiel (DSD, 2007)

Network-on-Chip Architecture Exploration Framework. - Timo Schönwald; Jochen Zimmermann; Oliver Bringmann 001; Wolfgang Rosenstiel (DSD, 2009)

Parallel matching-based estimation - a case study on three different hardware architectures. - Benjamin Ranft; Timo Schönwald; Bernd Kitt (Intelligent Vehicles Symposium, 2011)

Stereo depth map computation on a Tilera TILEPro64 embedded multicore processor. - Timo Schönwald; Alexander Koch 003; Benjamin Ranft; Alexander Viehl; Oliver Bringmann 001; Wolfgang Rosenstiel (DASIP, 2012)

Distance-Constrained Force-Directed Process Mapping for MPSoC Architectures. - Timo Schönwald; Alexander Viehl; Oliver Bringmann 001; Wolfgang Rosenstiel (DSD, 2012)

Latency-Optimized Force-directed Process Mapping for MPSoC Architectures. - Timo Schönwald; Benjamin Ranft; Oliver Bringmann 001; Wolfgang Rosenstiel (MBMV, 2012)

Optimized software mapping for advanced driver assistance systems. - Timo Schönwald; Alexander Viehl; Oliver Bringmann 001; Wolfgang Rosenstiel (SIES, 2012)

Shared memory aware MPSoC software deployment. - Timo Schönwald; Alexander Viehl; Oliver Bringmann 001; Wolfgang Rosenstiel (DATE, 2013)

Applikationsspezifische Optimierung der Kommunikation in Mehrkern-Architekturen für eingebettete Systeme. - Timo Schönwald (Verlag Dr. Hut, 2013)