A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms. - Ralf König 001; Timo Stripf; Jürgen Becker 001 (DATE, 2008)

KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture. - Ralf König 001; Lars Bauer; Timo Stripf; Muhammad Shafique 001; Waheed Ahmed; Jürgen Becker 001; Jörg Henkel (DATE, 2010)

A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors. - Ralf König 001; Timo Stripf; Jan Heisswolf; Jürgen Becker 001 (IPDPS Workshops, 2011)

Architecture design space exploration of run-time scalable issue-width processors. - Ralf König 001; Timo Stripf; Jan Heisswolf; Jürgen Becker 001 (ICSAMOS, 2011)

A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors. - Timo Stripf; Ralf König 001; Jürgen Becker 001 (ICSAMOS, 2011)

A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems. - Timo Stripf; Oliver Oey; Thomas Bruckschlögl; Ralf König 001; George Goulas; Panayiotis Alefragis; Nikolaos S. Voros; Jordy Potman; Kim Sunesen; Steven Derrien; Olivier Sentieys; Jürgen Becker 001 (CSE, 2012)

A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture. - Timo Stripf; Ralf König 001; Jürgen Becker 001 (DATE, 2012)

From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach. - Jürgen Becker 001; Timo Stripf; Oliver Oey; Michael Hübner 001; Steven Derrien; Daniel Ménard; Olivier Sentieys; Gerard K. Rauwerda; Kim Sunesen; Nikolaos Kavvadias; Kostas Masselos; George Goulas; et al. (DSD, 2012)

A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files. - Timo Stripf; Ralf König 001; Patrick Rieder; Jürgen Becker 001 (IPDPS Workshops, 2012)

A flexible approach for compiling scilab to reconfigurable multi-core embedded systems. - Timo Stripf; Oliver Oey; Thomas Bruckschlögl; Ralf König 001; Michael Hübner 001; Jürgen Becker 001; Gerard K. Rauwerda; Kim Sunesen; Nikolaos Kavvadias; Grigoris Dimitroulakos; Kostas Masselos; Dimitrios Kritharidis; et al. (ReCoSoC, 2012)

From Scilab to multicore embedded systems: Algorithms and methodologies. - George Goulas; Panayiotis Alefragis; Nikolaos S. Voros; Christos Valouxis; Christos Gogos; Nikolaos Kavvadias; Grigoris Dimitroulakos; Kostas Masselos; Diana Göhringer; Steven Derrien; Daniel Ménard; Olivier Sentieys; et al. (ICSAMOS, 2012)

Coarse-Grain Optimization and Code Generation for Embedded Multicore Systems. - George Goulas; Christos Valouxis; Panayiotis Alefragis; Nikolaos S. Voros; Christos Gogos; Oliver Oey; Timo Stripf; Thomas Bruckschlögl; Jürgen Becker 001; Ali El Moussawi; Maxime Naullet; Tomofumi Yuki (DSD, 2013)

A flexible implementation of the PSO algorithm for fine- and coarse-grained reconfigurable embedded systems. - Michael Rückauer; Daniel M. Muñoz; Timo Stripf; Oliver Oey; Carlos H. Llanos; Jürgen Becker 001 (ReConFig, 2013)

Compiling Scilab to high performance embedded multicore systems. - Timo Stripf; Oliver Oey; Thomas Bruckschlögl; Jürgen Becker 001; Gerard K. Rauwerda; Kim Sunesen; George Goulas; Panayiotis Alefragis; Nikolaos S. Voros; Steven Derrien; Olivier Sentieys; Nikolaos Kavvadias; et al. (Microprocess. Microsystems, 2013)

Softwareframework für Prozessoren mit variablen Befehlssatzarchitekturen. - Timo Stripf (2013)

Profile-Guided Compilation of Scilab Algorithms for Multiprocessor Systems. - Jürgen Becker 001; Thomas Bruckschlögl; Oliver Oey; Timo Stripf; George Goulas; Nick Raptis; Christos Valouxis; Panayiotis Alefragis; Nikolaos S. Voros; Christos Gogos (ARC, 2014)

A Hierarchical Architecture Description for Flexible Multicore System Simulation. - Thomas Bruckschlögl; Oliver Oey; Michael Rückauer; Timo Stripf; Jürgen Becker 001 (ISPA, 2014)

WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach. - Steven Derrien; Isabelle Puaut; Panayiotis Alefragis; Marcus Bednara; Harald Bucher; Clément David; Yann Debray; Umut Durak; Imen Fassi; Christian Ferdinand; Damien Hardy; Angeliki Kritikakou; et al. (DATE, 2017)

A WCET-aware parallel programming model for predictability enhanced multi-core architectures. - Simon Reder; Leonard Masing; Harald Bucher; Timon D. ter Braak; Timo Stripf; Jürgen Becker 001 (DATE, 2018)

Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications. - Simon Reder; Fabian Kempf; Harald Bucher; Jürgen Becker 001; Panayiotis Alefragis; Nikolaos S. Voros; Stefanos Skalistis; Steven Derrien; Isabelle Puaut; Oliver Oey; Timo Stripf; Christian Ferdinand; et al. (J. Aerosp. Inf. Syst., 2019)

Embedded Multi-Core Code Generation with Cross-Layer Parallelization. - Oliver Oey; Michael Hübner 001; Timo Stripf; Jürgen Becker 001 (PARMA-DITAM, 2024)