Timothy Hayes

Orcid: 0000-0002-8575-4914

Affiliations:
  • Barcelona Supercomputing Center, Spain


According to our database1, Timothy Hayes authored at least 11 papers between 2012 and 2021.

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Timeline

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Bibliography

2021
Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
The gem5 Simulator: Version 20.0+.
CoRR, 2020

2017
An Integrated Vector-Scalar Design on an In-Order ARM Core.
ACM Trans. Archit. Code Optim., 2017

2016
Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory.
Comput. Sci. Eng., 2016

Future Vector Microprocessor Extensions for Data Aggregations.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Towards low-power embedded vector processor.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Novel vector architectures for data management.
PhD thesis, 2015

VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015


2012
Vector Extensions for Decision Support DBMS Acceleration.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012


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