Optimization of MOS amplifier performance through channel length and inversion level selection. - Timothy M. Hollis; David J. Comer; Donald T. Comer (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

Mitigating ISI Through Self-Calibrating Continuous-Time Equalization. - Timothy M. Hollis; David J. Comer; Donald T. Comer (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Jittery Signal Generation for High-Speed Interconnect Simulation. - Timothy M. Hollis (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Data Bus Inversion in High-Speed Memory Applications. - Timothy M. Hollis (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

25.3 An 8Gb GDDR6X DRAM Achieving 22Gb/s/pin with Single-Ended PAM4 Signaling. - Timothy M. Hollis; Ronny Schneider; Martin Brox; Thomas Hein; Wolfgang Spirkl; Martin Bach; Mani Balakrishnan; Stefan Dietrich; Fabien Funfrock; Milena Ivanov; Natalija Jovanovic; Maksim Kuzmenka; et al. (ISSCC, 2021)

An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling. - Timothy M. Hollis; Ronny Schneider; Martin Brox; Thomas Hein; Wolfgang Spirkl; Martin Bach; Mani Balakrishnan; Stefan Dietrich; Fabien Funfrock; Milena Ivanov; Natalija Jovanovic; Maksim Kuzmenka; et al. (IEEE J. Solid State Circuits, 2022)