Compiler Directed Early Register Release. - Timothy M. Jones 001; Michael F. P. O'Boyle; Jaume Abella 001; Antonio González 001; Oguz Ergin (IEEE PACT, 2005)

Software Directed Issue Queue Power Reduction. - Timothy M. Jones 001; Michael F. P. O'Boyle; Jaume Abella 001; Antonio González 001 (HPCA, 2005)

Compiler-directed energy savings in superscalar processors. - Timothy M. Jones 001 (2006)

Microarchitectural Design Space Exploration Using an Architecture-Centric Approach. - Christophe Dubach; Timothy M. Jones 001; Michael F. P. O'Boyle (MICRO, 2007)

Exploring and predicting the architecture/optimising compiler co-design space. - Christophe Dubach; Timothy M. Jones 001; Michael F. P. O'Boyle (CASES, 2008)

Instruction Cache Energy Saving Through Compiler Way-Placement. - Timothy M. Jones 001; Sandro Bartolini; Bruno De Bus; John Cavazos; Michael F. P. O'Boyle (DATE, 2008)

Rapid early-stage microarchitecture design using predictive models. - Christophe Dubach; Timothy M. Jones 001; Michael F. P. O'Boyle (ICCD, 2009)

Portable compiler optimisation across embedded programs and microarchitectures using machine learning. - Christophe Dubach; Timothy M. Jones 001; Edwin V. Bonilla; Grigori Fursin; Michael F. P. O'Boyle (MICRO, 2009)

Exploring the limits of early register release: Exploiting compiler analysis. - Timothy M. Jones 001; Michael F. P. O'Boyle; Jaume Abella 001; Antonio González 001; Oguz Ergin (ACM Trans. Archit. Code Optim., 2009)

Energy-efficient register caching with compiler assistance. - Timothy M. Jones 001; Michael F. P. O'Boyle; Jaume Abella 001; Antonio González 001; Oguz Ergin (ACM Trans. Archit. Code Optim., 2009)

A Predictive Model for Dynamic Microarchitectural Adaptivity Control. - Christophe Dubach; Timothy M. Jones 001; Edwin V. Bonilla; Michael F. P. O'Boyle (MICRO, 2010)

Beforehand Migration on D-NUCA Caches. - Javier Lira; Timothy M. Jones 001; Carlos Molina; Antonio González 001 (PACT, 2011)

A reconfigurable cache architecture for energy efficiency. - Karthik T. Sundararajan; Timothy M. Jones 001; Nigel P. Topham (Conf. Computing Frontiers, 2011)

Link-time optimization for power efficiency in a tagless instruction cache. - Timothy M. Jones 001; Sandro Bartolini; Jonas Maebe; Dominique Chanet (CGO, 2011)

Smart cache: A self adaptive cache architecture for energy efficiency. - Karthik T. Sundararajan; Timothy M. Jones 001; Nigel P. Topham (ICSAMOS, 2011)

An Empirical Architecture-Centric Approach to Microarchitectural Design Space Exploration. - Christophe Dubach; Timothy M. Jones 001; Michael F. P. O'Boyle (IEEE Trans. Computers, 2011)

Compiler Directed Issue Queue Energy Reduction. - Timothy M. Jones 001; Michael F. P. O'Boyle; Jaume Abella 001; Antonio González 001 (Trans. High Perform. Embed. Archit. Compil., 2011)

Energy-efficient cache partitioning for future CMPs. - Karthik T. Sundararajan; Timothy M. Jones 001; Nigel P. Topham (PACT, 2012)

HELIX: automatic parallelization of irregular programs for chip multiprocessing. - Simone Campanoni; Timothy M. Jones 001; Glenn H. Holloway; Vijay Janapa Reddi; Gu-Yeon Wei; David M. Brooks (CGO, 2012)

The HELIX project: overview and directions. - Simone Campanoni; Timothy M. Jones 001; Glenn H. Holloway; Gu-Yeon Wei; David M. Brooks (DAC, 2012)

Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs. - Karthik T. Sundararajan; Vasileios Porpodas; Timothy M. Jones 001; Nigel P. Topham; Björn Franke (HPCA, 2012)

Helix: Making the Extraction of Thread-Level Parallelism Mainstream. - Simone Campanoni; Timothy M. Jones 001; Glenn H. Holloway; Gu-Yeon Wei; David M. Brooks (IEEE Micro, 2012)

The migration prefetcher: Anticipating data promotion in dynamic NUCA caches. - Javier Lira; Timothy M. Jones 001; Carlos Molina; Antonio González 001 (ACM Trans. Archit. Code Optim., 2012)

Exploring and Predicting the Effects of Microarchitectural Parameters and Compiler Optimizations on Performance and Energy. - Christophe Dubach; Timothy M. Jones 001; Michael F. P. O'Boyle (ACM Trans. Embed. Comput. Syst., 2012)

RECAP: Region-Aware Cache Partitioning. - Karthik T. Sundararajan; Timothy M. Jones 001; Nigel P. Topham (ICCD, 2013)

Full system simulation of optically interconnected chip multiprocessors using gem5. - Anouk Van Laer; Timothy M. Jones 001; Philip M. Watts (OFC/NFOEC, 2013)

The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation. - Karthik T. Sundararajan; Timothy M. Jones 001; Nigel P. Topham (Int. J. Parallel Program., 2013)

Dynamic microarchitectural adaptation using machine learning. - Christophe Dubach; Timothy M. Jones 001; Edwin V. Bonilla (ACM Trans. Archit. Code Optim., 2013)

ALLARM: Optimizing sparse directories for thread-local data. - Amitabha Roy 002; Timothy M. Jones 001 (DATE, 2014)

HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs. - Simone Campanoni; Kevin Brownell; Svilen Kanev; Timothy M. Jones 001; Gu-Yeon Wei; David M. Brooks (ISCA, 2014)

Towards zero latency photonic switching in shared memory networks. - Muhammad Ridwan Madarbux; Anouk Van Laer; Philip M. Watts; Timothy M. Jones 001 (Concurr. Comput. Pract. Exp., 2014)

Throttling Automatic Vectorization: When Less is More. - Vasileios Porpodas; Timothy M. Jones 001 (PACT, 2015)

PSLP: padded SLP automatic vectorization. - Vasileios Porpodas; Alberto Magni; Timothy M. Jones 001 (CGO, 2015)

Coherence based message prediction for optically interconnected chip multiprocessors. - Anouk Van Laer; Chamath Ellawala; Muhammad Ridwan Madarbux; Philip M. Watts; Timothy M. Jones 001 (DATE, 2015)

REPAIR: Hard-error recovery via re-execution. - Jyothish Soman; Negar Miralaei; Alan Mycroft; Timothy M. Jones 001 (DFTS, 2015)

COMET: communication-optimised multi-threaded error-detection technique. - Konstantina Mitropoulou; Vasileios Porpodas; Timothy M. Jones 001 (CASES, 2016)

Performance implications of transient loop-carried data dependences in automatically parallelized loops. - Niall Murphy; Timothy M. Jones 001; Robert D. Mullins; Simone Campanoni (CC, 2016)

Energy Efficient And Low Latency Interconnection Network For Multicast Invalidates In Shared Memory Systems. - Muhammad Ridwan Madarbux; Anouk Van Laer; Philip M. Watts; Timothy M. Jones 001 (AISTECS@HiPEAC, 2016)

Graph Prefetching Using Data Structure Knowledge. - Sam Ainsworth; Timothy M. Jones 001 (ICS, 2016)

Lynx: Using OS and Hardware Support for Fast Fine-Grained Inter-Core Communication. - Konstantina Mitropoulou; Vasileios Porpodas; Xiaochun Zhang; Timothy M. Jones 001 (ICS, 2016)

Enhancing the L1 Data Cache Design to Mitigate HCI. - Alejandro Valero; Negar Miralaei; Salvador Petit; Julio Sahuquillo; Timothy M. Jones 001 (IEEE Comput. Archit. Lett., 2016)

Software prefetching for indirect memory accesses. - Sam Ainsworth; Timothy M. Jones 001 (CGO, 2017)

High performance fault tolerance through predictive instruction re-execution. - Jyothish Soman; Timothy M. Jones 001 (DFT, 2017)

Automatically accelerating non-numerical programs by architecture-compiler co-design. - Simone Campanoni; Kevin Brownell; Svilen Kanev; Timothy M. Jones 001; Gu-Yeon Wei; David M. Brooks (Commun. ACM, 2017)

On Microarchitectural Mechanisms for Cache Wearout Reduction. - Alejandro Valero; Negar Miralaei; Salvador Petit; Julio Sahuquillo; Timothy M. Jones 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An Event-Triggered Programmable Prefetcher for Irregular Workloads. - Sam Ainsworth; Timothy M. Jones 001 (ASPLOS, 2018)

Parallel Error Detection Using Heterogeneous Cores. - Sam Ainsworth; Timothy M. Jones 001 (DSN, 2018)

Software Prefetching for Indirect Memory Accesses: A Microarchitectural Perspective. - Sam Ainsworth; Timothy M. Jones 001 (ACM Trans. Comput. Syst., 2018)

Janus: Statically-Driven and Profile-Guided Automatic Dynamic Binary Parallelisation. - Ruoyu Zhou; Timothy M. Jones 001 (CGO, 2019)

ParaMedic: Heterogeneous Parallel Error Correction. - Sam Ainsworth; Timothy M. Jones 001 (DSN, 2019)

CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety. - Hongyan Xia; Jonathan Woodruff; Sam Ainsworth; Nathaniel Wesley Filardo; Michael Roe; Alexander Richardson 001; Peter Rugg; Peter G. Neumann; Simon W. Moore; Robert N. M. Watson; Timothy M. Jones 001 (MICRO, 2019)

On Verifying Timed Hyperproperties. - Hsi-Ming Ho; Ruoyu Zhou; Timothy M. Jones 001 (TIME, 2019)

The janus triad: exploiting parallelism through dynamic binary modification. - Ruoyu Zhou; George Wort; Márton Erdos; Timothy M. Jones 001 (VEE, 2019)

The Guardian Council: Parallel Programmable Hardware Security. - Sam Ainsworth; Timothy M. Jones 001 (ASPLOS, 2020)

HALO: post-link heap-layout optimisation. - Joe Savage; Timothy M. Jones 001 (CGO, 2020)

MuonTrap: Preventing Cross-Domain Spectre-Like Attacks by Capturing Speculative State. - Sam Ainsworth; Timothy M. Jones 001 (ISCA, 2020)

Prefetching in functional languages. - Sam Ainsworth; Timothy M. Jones 001 (ISMM, 2020)

MarkUs: Drop-in use-after-free prevention for low-level languages. - Sam Ainsworth; Timothy M. Jones 001 (SP, 2020)

Cornucopia: Temporal Safety for CHERI Heaps. - Nathaniel Wesley Filardo; Brett F. Gutstein; Jonathan Woodruff; Sam Ainsworth; Lucian Paul-Trifu; Brooks Davis; Hongyan Xia; Edward Tomasz Napierala; Alexander Richardson 001; John Baldwin; David Chisnall; Jessica Clarke 001; et al. (SP, 2020)

The gem5 Simulator: Version 20.0+. - Jason Lowe-Power; Abdul Mutaal Ahmad; Ayaz Akram; Mohammad Alian; Rico Amslinger; Matteo Andreozzi; Adrià Armejach; Nils Asmussen; Srikant Bharadwaj; Gabe Black; Gedare Bloom; Bobby R. Bruce; et al. (CoRR, 2020)

Duplo: a framework for OCaml post-link optimisation. - Nándor Licker; Timothy M. Jones 001 (Proc. ACM Program. Lang., 2020)

Software Prefetching for Unstructured Mesh Applications. - Ioan Hadade; Timothy M. Jones 001; Feng Wang 021; Luca di Mare (ACM Trans. Parallel Comput., 2020)

Cinnamon: A Domain-Specific Language for Binary Profiling and Monitoring. - Mahwish Arif; Ruoyu Zhou; Hsi-Ming Ho; Timothy M. Jones 001 (CGO, 2021)

ParaDox: Eliminating Voltage Margins via Heterogeneous Fault Tolerance. - Sam Ainsworth; Lionel Zoubritzky; Alan Mycroft; Timothy M. Jones 001 (HPCA, 2021)

Quantifying the Semantic Gap Between Serial and Parallel Programming. - Xiaochun Zhang; Timothy M. Jones 001; Simone Campanoni (IISWC, 2021)

Vector Runahead. - Ajeya Naithani; Sam Ainsworth; Timothy M. Jones 001; Lieven Eeckhout (ISCA, 2021)

Speculative Vectorisation with Selective Replay. - Peng Sun; Giacomo Gabrielli; Timothy M. Jones 001 (ISCA, 2021)

Compendia: reducing virtual-memory costs via selective densification. - Sam Ainsworth; Timothy M. Jones 001 (ISMM, 2021)

Timed hyperproperties. - Hsi-Ming Ho; Ruoyu Zhou; Timothy M. Jones 001 (Inf. Comput., 2021)

MineSweeper: a "clean sweep" for drop-in use-after-free prevention. - Márton Erdos; Sam Ainsworth; Timothy M. Jones 001 (ASPLOS, 2022)

Vector Runahead for Indirect Memory Accesses. - Ajeya Naithani; Sam Ainsworth; Timothy M. Jones 001; Lieven Eeckhout (IEEE Micro, 2022)

Dynamic Allocation of Processor Cores to Graph Applications on Commodity Servers. - Lucia Pons; Julio Sahuquillo; Timothy M. Jones 001 (PACT, 2023)

Decoupled Vector Runahead. - Ajeya Naithani; Jaime Roelandts; Sam Ainsworth; Timothy M. Jones 001; Lieven Eeckhout (MICRO, 2023)

OptiWISE: Combining Sampling and Instrumentation for Granular CPI Analysis. - Yuxin Guo; Alexandra W. Chadwick; Márton Erdos; Utpal Bora 003; Ilias Vougioukas; Giacomo Gabrielli; Timothy M. Jones 001 (CGO, 2024)

Advanced Dynamic Scalarisation for RISC-V GPGPUs. - Matthew Naylor; Alexandre Joannou; A. Theodore Markettos; Paul Metzger; Simon W. Moore; Timothy M. Jones 001 (ICCD, 2024)

Scalar Vector Runahead. - Jaime Roelandts; Ajeya Naithani; Sam Ainsworth; Timothy M. Jones 001; Lieven Eeckhout (MICRO, 2024)

Decoupled Vector Runahead for Prefetching Nested Memory-Access Chains. - Ajeya Naithani; Jaime Roelandts; Sam Ainsworth; Timothy M. Jones 001; Lieven Eeckhout (IEEE Micro, 2024)

A Deep Technical Review of nZDC Fault Tolerance. - Minli Liao; Sam Ainsworth; Lev Mukhanov; Timothy M. Jones 001 (CC, 2025)

Janitizer: Rethinking Binary Tools for Practical and Comprehensive Security. - Mahwish Arif; Sam Ainsworth; Timothy M. Jones 001 (CGO, 2025)

Parallaft: Runtime-Based CPU Fault Tolerance via Heterogeneous Parallelism. - Boyue Zhang; Sam Ainsworth; Lev Mukhanov; Timothy M. Jones 001 (CGO, 2025)

ParaVerser: Harnessing Heterogeneous Parallelism for Affordable Fault Detection in Data Centers. - Minli Julie Liao; Sam Ainsworth; Lev Mukhanov; Adrián Barredo; Markos Kynigos; Timothy M. Jones 001 (DSN, 2025)

Mascot: Predicting Memory Dependencies and Opportunities for Speculative Memory Bypassing. - Karl H. Mose; Sebastian S. Kim; Alberto Ros 001; Timothy M. Jones 001; Robert D. Mullins (HPCA, 2025)

Adaptive CHERI Compartmentalization for Heterogeneous Accelerators. - Jianyi Cheng; A. Theodore Markettos; Alexandre Joannou; Paul Metzger; Matthew Naylor; Peter Rugg; Timothy M. Jones 001 (ISCA, 2025)

The Future of Instruction-Level Parallelism (ILP). - Alexandra W. Chadwick; Márton Erdos; Utpal Bora 003; Akshay Bhosale; Bob Lytton; Yuxin Guo; Richard Cooper; Giacomo Gabrielli; Timothy M. Jones 001 (ISPASS, 2025)

MEEK: Re-thinking Heterogeneous Parallel Error Detection Architecture for Real-World OoO Superscalar Processors. - Zhe Jiang; Minli Liao; Sam Ainsworth; Dean You; Timothy M. Jones 001 (CoRR, 2025)

FireGuard: A Generalized Microarchitecture for Fine-Grained Security Analysis on OoO Superscalar Cores. - Zhe Jiang; Sam Ainsworth; Timothy M. Jones 001 (CoRR, 2025)