Wireless interconnects for clock distribution. - Brian A. Floyd; Xiaoling Guo; James Caserta; Timothy O. Dickson; Chih-Ming Hung; Kihong Kim; Kenneth K. O (Timing Issues in the Specification and Synthesis of Digital Systems, 2002)

A 1.5V 20/30 Gb/s CMOS backplane driver with digital pre-emphasis. - Paul Westergaard; Timothy O. Dickson; Sorin P. Voinigescu (CICC, 2004)

Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes. - Sorin P. Voinigescu; Timothy O. Dickson; Theodoros Chalvatzis; Altan Hazneci; Ekaterina Laskin; Rudy Beerkens; Imran Khalid; Edward S. Rogers Sr. (CICC, 2005)

The feasibility of on-chip interconnection using antennas. - Kenneth K. O; Kihong Kim; Brian A. Floyd; Jesal Mehta; Hyun Yoon; Chih-Ming Hung; Daniel F. Bravo; Timothy O. Dickson; Xiaoling Guo; Ran Li 001; Narasimhan Trichy; James Caserta; et al. (ICCAD, 2005)

A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic. - Timothy O. Dickson; Rudy Beerkens; Sorin P. Voinigescu (IEEE J. Solid State Circuits, 2005)

An 80-Gb/s 231-1 pseudorandom binary sequence generator in SiGe BiCMOS technology. - Timothy O. Dickson; Ekaterina Laskin; Imran Khalid; Rudy Beerkens; Jingqiong Xie; Boris Karajica; Sorin P. Voinigescu (IEEE J. Solid State Circuits, 2005)

Silicon Integrated Circuits Incorporating Antennas. - Kenneth K. O; Kihong Kim; Brian A. Floyd; Jesal Mehta; Hyun Yoon; Chih-Ming Hung; Daniel F. Bravo; Timothy O. Dickson; Xiaoling Guo; Ran Li 001; Narasimhan Trichy; James Caserta; et al. (CICC, 2006)

The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks. - Timothy O. Dickson; Kenneth H. K. Yau; Theodoros Chalvatzis; Alain M. Mangan; Ekaterina Laskin; Rudy Beerkens; Paul Westergaard; Mihai Tazlauanu; Ming-Ta Yang; Sorin P. Voinigescu (IEEE J. Solid State Circuits, 2006)

Towards a sub-2.5V, 100-Gb/s Serial Transceiver. - Sorin P. Voinigescu; Ricardo Andres Aroca; Timothy O. Dickson; Sean T. Nicolson; Theodoros Chalvatzis; Pascal Chevalier 002; Patrice Garcia; Christophe Gamier; Bernard Sautreuil (CICC, 2007)

Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS. - Timothy O. Dickson; Sorin P. Voinigescu (IEEE J. Solid State Circuits, 2007)

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS. - John F. Bulzacchelli; Timothy O. Dickson; Zeynep Toprak Deniz; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Sergey V. Rylov; Daniel J. Friedman (ISSCC, 2009)

A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS. - Yong Liu 023; Byungsub Kim; Timothy O. Dickson; John F. Bulzacchelli; Daniel J. Friedman (ISSCC, 2009)

A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology. - Timothy O. Dickson; John F. Bulzacchelli; Daniel J. Friedman (IEEE J. Solid State Circuits, 2009)

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS. - Byungsub Kim; Yong Liu 023; Timothy O. Dickson; John F. Bulzacchelli; Daniel J. Friedman (IEEE J. Solid State Circuits, 2009)

A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS. - Ankur Agrawal; John F. Bulzacchelli; Timothy O. Dickson; Yong Liu 023; José A. Tierno; Daniel J. Friedman (ISSCC, 2012)

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS. - Ankur Agrawal; John F. Bulzacchelli; Timothy O. Dickson; Yong Liu 023; José A. Tierno; Daniel J. Friedman (IEEE J. Solid State Circuits, 2012)

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Bing Dang; Cornelia K. Tsang; Paul S. Andry; John F. Bulzacchelli; Herschel A. Ainspan; Xiaoxiong Gu; Lavanya Turlapati; Michael P. Beakes; Benjamin D. Parker; et al. (IEEE J. Solid State Circuits, 2012)

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Christian W. Baks; et al. (CICC, 2014)

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. - Timothy O. Dickson; Yong Liu 023; Ankur Agrawal; John F. Bulzacchelli; Herschel A. Ainspan; Zeynep Toprak Deniz; Benjamin D. Parker; Mounir Meghelli; Daniel J. Friedman (CICC, 2015)

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; et al. (IEEE J. Solid State Circuits, 2015)

A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. - Timothy O. Dickson; Yong Liu 023; Ankur Agrawal; John F. Bulzacchelli; Herschel A. Ainspan; Zeynep Toprak Deniz; Benjamin D. Parker; Michael P. Beakes; Mounir Meghelli; Daniel J. Friedman (IEEE J. Solid State Circuits, 2016)

6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS. - Timothy O. Dickson; Herschel A. Ainspan; Mounir Meghelli (ISSCC, 2017)

A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS. - Jonathan E. Proesel; Zeynep Toprak Deniz; Alessandro Cevrero; Ilter Özkaya; Seongwon Kim; Daniel M. Kuchta; Sungjae Lee 005; Sergey V. Rylov; Herschel A. Ainspan; Timothy O. Dickson; John F. Bulzacchelli; Mounir Meghelli (IEEE J. Solid State Circuits, 2018)

A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS. - Zeynep Toprak Deniz; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Timothy O. Dickson; Michael P. Beakes; Mounir Meghelli (ISSCC, 2019)

Multi-Wavelength Optical Transceivers Integrated on Node (MOTION). - Daniel M. Kuchta; Jonathan E. Proesel; Fuad E. Doany; Wooram Lee; Timothy O. Dickson; Herschel A. Ainspan; Mounir Meghelli; Petar K. Pepeljugoski; Xiaoxiong Gu; Michael P. Beakes; Mark Schultz; Marc Taubenblatt; et al. (OFC, 2019)

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS. - Zeynep Toprak Deniz; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Timothy O. Dickson; Michael P. Beakes; Mounir Meghelli (IEEE J. Solid State Circuits, 2020)

Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS". - Zeynep Toprak Deniz; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Timothy O. Dickson; Michael P. Beakes; Mounir Meghelli (IEEE J. Solid State Circuits, 2020)

A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Troy J. Beukema; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (VLSI Technology and Circuits, 2022)

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. - Serdar S. Yonar; Pier Andrea Francese; Matthias Brändli; Marcel A. Kossel; Thomas Morf; Jonathan E. Proesel; Sergey V. Rylov; Herschel A. Ainspan; Martin Cochet; Zeynep Toprak Deniz; Timothy O. Dickson; Troy J. Beukema; et al. (VLSI Technology and Circuits, 2022)

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Troy J. Beukema; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (IEEE J. Solid State Circuits, 2023)

Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; John F. Bulzacchelli; Marcel A. Kossel; Pier Andrea Francese; Thomas Morf; Jonathan E. Proesel; Herschel A. Ainspan; Matthias Brändli; Mounir Meghelli (CICC, 2024)

A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1 mathrm{V}_{ text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS. - Zeynep Toprak Deniz; Timothy O. Dickson; Martin Cochet; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Matthias Brändli; Thomas Morf; Michael P. Beakes; Mounir Meghelli (VLSI Technology and Circuits, 2024)