1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus. - Jared L. Zerbe; Pak Shing Chau; Carl W. Werner; Timothy P. Thrush; H. J. Liaw; Bruno W. Garlepp; Kevin S. Donnelly (IEEE J. Solid State Circuits, 2001)

Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell. - Jared L. Zerbe; Carl W. Werner; Vladimir Stojanovic; Fred Chen; Jason Wei; Grace Tsang; Dennis Kim; William F. Stonecypher; Andrew Ho; Timothy P. Thrush; Ravi T. Kollipara; Mark A. Horowitz; et al. (IEEE J. Solid State Circuits, 2003)